| /openbmc/linux/drivers/virt/vboxguest/ |
| H A D | vboxguest_core.c | 549 req->or_mask = fixed_events; in vbg_reset_host_event_filter()
576 u32 or_mask, u32 not_mask, in vbg_set_session_event_filter() argument
616 req->or_mask = or_mask; in vbg_set_session_event_filter()
617 req->not_mask = ~or_mask; in vbg_set_session_event_filter()
655 req->or_mask = 0; in vbg_reset_host_capabilities()
696 req->or_mask = caps; in vbg_set_host_capabilities()
1571 u32 or_mask, not_mask; in vbg_ioctl_change_filter_mask() local
1576 or_mask = filter->u.in.or_mask; in vbg_ioctl_change_filter_mask()
1596 or_mask = caps->u.in.or_mask; in vbg_ioctl_acquire_guest_capabilities()
1612 u32 or_mask, not_mask; in vbg_ioctl_change_guest_capabilities() local
[all …]
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| H A D | vmmdev.h | 191 u32 or_mask; member
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | soc15.h | 42 u32 or_mask; member
93 #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \ argument
94 { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
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| H A D | soc15.c | 460 tmp = entry->or_mask; in soc15_program_register_sequence()
466 tmp |= (entry->or_mask & entry->and_mask); in soc15_program_register_sequence()
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| H A D | amdgpu_device.c | 949 u32 tmp, reg, and_mask, or_mask; in amdgpu_device_program_register_sequence() local
958 or_mask = registers[i + 2]; in amdgpu_device_program_register_sequence()
961 tmp = or_mask; in amdgpu_device_program_register_sequence()
966 tmp |= (or_mask & and_mask); in amdgpu_device_program_register_sequence()
968 tmp |= or_mask; in amdgpu_device_program_register_sequence()
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| /openbmc/linux/include/uapi/linux/ |
| H A D | vboxguest.h | 247 __u32 or_mask; member
269 __u32 or_mask; member
291 __u32 or_mask; member
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| /openbmc/u-boot/board/micronas/vct/ |
| H A D | gpio.c | 34 static void clrsetbits(u32 addr, u32 and_mask, u32 or_mask) in clrsetbits() argument
36 reg_write(addr, (reg_read(addr) & ~and_mask) | or_mask); in clrsetbits()
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| /openbmc/linux/drivers/staging/media/atomisp/pci/ |
| H A D | ia_css_pipe_public.h | 347 unsigned int or_mask,
368 unsigned int *or_mask,
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| H A D | sh_css_sp.c | 1538 event_irq_mask_init.or_mask = IA_CSS_EVENT_TYPE_ALL; in sh_css_event_init_irq_mask()
1555 unsigned int or_mask, in ia_css_pipe_set_irq_mask() argument
1576 IA_CSS_LOG("or_mask=%x, and_mask=%x", or_mask, and_mask); in ia_css_pipe_set_irq_mask()
1577 event_irq_mask.or_mask = (uint16_t)or_mask; in ia_css_pipe_set_irq_mask()
1595 unsigned int *or_mask, in ia_css_event_get_irq_mask() argument
1620 if (or_mask) in ia_css_event_get_irq_mask()
1621 *or_mask = event_irq_mask.or_mask; in ia_css_event_get_irq_mask()
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| H A D | sh_css_internal.h | 754 u16 or_mask; member
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| /openbmc/linux/arch/mips/include/asm/mach-rc32434/ |
| H A D | rb.h | 61 extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
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| /openbmc/linux/arch/mips/rb532/ |
| H A D | devices.c | 40 void set_latch_u5(unsigned char or_mask, unsigned char nand_mask) in set_latch_u5() argument
46 dev3.state = (dev3.state | or_mask) & ~nand_mask; in set_latch_u5()
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| /openbmc/qemu/target/sh4/ |
| H A D | helper.c | 190 uint8_t or_mask = 0, and_mask = (uint8_t) - 1; in update_itlb_use() local
198 or_mask = 0x80; in update_itlb_use()
202 or_mask = 0x50; in update_itlb_use()
205 or_mask = 0x2c; in update_itlb_use()
210 env->mmucr |= (or_mask << 24); in update_itlb_use()
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| /openbmc/linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_combios.c | 2973 or_mask = RBIOS32(index); in radeon_combios_external_tmds_setup()
2988 or_mask = RBIOS32(index); in radeon_combios_external_tmds_setup()
3040 or_mask = RBIOS32(offset); in combios_parse_mmio_table()
3044 tmp |= or_mask; in combios_parse_mmio_table()
3050 or_mask = RBIOS32(offset); in combios_parse_mmio_table()
3054 tmp |= or_mask; in combios_parse_mmio_table()
3102 uint32_t and_mask, or_mask; in combios_parse_pll_table() local
3121 tmp |= or_mask; in combios_parse_pll_table()
3216 tmp |= or_mask; in combios_parse_ram_reset_table()
3219 or_mask = val << 24; in combios_parse_ram_reset_table()
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| H A D | radeon_device.c | 206 u32 tmp, reg, and_mask, or_mask; in radeon_program_register_sequence() local
215 or_mask = registers[i + 2]; in radeon_program_register_sequence()
218 tmp = or_mask; in radeon_program_register_sequence()
222 tmp |= or_mask; in radeon_program_register_sequence()
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| /openbmc/linux/drivers/iio/adc/ |
| H A D | mt6577_auxadc.c | 100 u32 or_mask, u32 and_mask) in mt6577_auxadc_mod_reg() argument
105 val |= or_mask; in mt6577_auxadc_mod_reg()
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| /openbmc/linux/drivers/net/ethernet/natsemi/ |
| H A D | ns83820.c | 1677 u32 or_mask = 0; local
1681 or_mask |= RFCR_AAU | RFCR_AAM;
1686 or_mask |= RFCR_AAM;
1691 val = (readl(rfcr) & and_mask) | or_mask;
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| /openbmc/linux/mm/ |
| H A D | mm_init.c | 81 unsigned long or_mask, add_mask; in mminit_verify_pageflags_layout() local
140 or_mask = (ZONES_MASK << ZONES_PGSHIFT) | in mminit_verify_pageflags_layout()
146 BUG_ON(or_mask != add_mask); in mminit_verify_pageflags_layout()
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| /openbmc/linux/drivers/gpu/drm/bridge/analogix/ |
| H A D | anx7625.c | 176 u8 offset, u8 and_mask, u8 or_mask) in anx7625_write_and_or() argument
185 offset, (val & and_mask) | (or_mask)); in anx7625_write_and_or()
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