1f5fbb83fSMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0 */
29d4fa1a1SMauro Carvalho Chehab /*
39d4fa1a1SMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem.
49d4fa1a1SMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation.
59d4fa1a1SMauro Carvalho Chehab *
69d4fa1a1SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it
79d4fa1a1SMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License,
89d4fa1a1SMauro Carvalho Chehab * version 2, as published by the Free Software Foundation.
99d4fa1a1SMauro Carvalho Chehab *
109d4fa1a1SMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT
119d4fa1a1SMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
129d4fa1a1SMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
139d4fa1a1SMauro Carvalho Chehab * more details.
149d4fa1a1SMauro Carvalho Chehab */
159d4fa1a1SMauro Carvalho Chehab
169d4fa1a1SMauro Carvalho Chehab #ifndef _SH_CSS_INTERNAL_H_
179d4fa1a1SMauro Carvalho Chehab #define _SH_CSS_INTERNAL_H_
189d4fa1a1SMauro Carvalho Chehab
199d4fa1a1SMauro Carvalho Chehab #include <system_global.h>
209d4fa1a1SMauro Carvalho Chehab #include <math_support.h>
219d4fa1a1SMauro Carvalho Chehab #include <type_support.h>
229d4fa1a1SMauro Carvalho Chehab #include <platform_support.h>
23c0891ac1SAlexey Dobriyan #include <linux/stdarg.h>
249d4fa1a1SMauro Carvalho Chehab
25641c2292SMauro Carvalho Chehab #if !defined(ISP2401)
269d4fa1a1SMauro Carvalho Chehab #include "input_formatter.h"
279d4fa1a1SMauro Carvalho Chehab #endif
289d4fa1a1SMauro Carvalho Chehab #include "input_system.h"
299d4fa1a1SMauro Carvalho Chehab
309d4fa1a1SMauro Carvalho Chehab #include "ia_css_types.h"
319d4fa1a1SMauro Carvalho Chehab #include "ia_css_acc_types.h"
329d4fa1a1SMauro Carvalho Chehab #include "ia_css_buffer.h"
339d4fa1a1SMauro Carvalho Chehab
349d4fa1a1SMauro Carvalho Chehab #include "ia_css_binary.h"
359d4fa1a1SMauro Carvalho Chehab #include "sh_css_firmware.h" /* not needed/desired on SP/ISP */
369d4fa1a1SMauro Carvalho Chehab #include "sh_css_legacy.h"
379d4fa1a1SMauro Carvalho Chehab #include "sh_css_defs.h"
389d4fa1a1SMauro Carvalho Chehab #include "sh_css_uds.h"
399d4fa1a1SMauro Carvalho Chehab #include "dma.h" /* N_DMA_CHANNEL_ID */
409d4fa1a1SMauro Carvalho Chehab #include "ia_css_circbuf_comm.h" /* Circular buffer */
419d4fa1a1SMauro Carvalho Chehab #include "ia_css_frame_comm.h"
429d4fa1a1SMauro Carvalho Chehab #include "ia_css_3a.h"
439d4fa1a1SMauro Carvalho Chehab #include "ia_css_dvs.h"
449d4fa1a1SMauro Carvalho Chehab #include "ia_css_metadata.h"
459d4fa1a1SMauro Carvalho Chehab #include "runtime/bufq/interface/ia_css_bufq.h"
469d4fa1a1SMauro Carvalho Chehab #include "ia_css_timer.h"
479d4fa1a1SMauro Carvalho Chehab
489d4fa1a1SMauro Carvalho Chehab /* TODO: Move to a more suitable place when sp pipeline design is done. */
499d4fa1a1SMauro Carvalho Chehab #define IA_CSS_NUM_CB_SEM_READ_RESOURCE 2
509d4fa1a1SMauro Carvalho Chehab #define IA_CSS_NUM_CB_SEM_WRITE_RESOURCE 1
519d4fa1a1SMauro Carvalho Chehab #define IA_CSS_NUM_CBS 2
529d4fa1a1SMauro Carvalho Chehab #define IA_CSS_CB_MAX_ELEMS 2
539d4fa1a1SMauro Carvalho Chehab
549d4fa1a1SMauro Carvalho Chehab /* Use case specific. index limited to IA_CSS_NUM_CB_SEM_READ_RESOURCE or
559d4fa1a1SMauro Carvalho Chehab * IA_CSS_NUM_CB_SEM_WRITE_RESOURCE for read and write respectively.
569d4fa1a1SMauro Carvalho Chehab * TODO: Enforce the limitation above.
579d4fa1a1SMauro Carvalho Chehab */
589d4fa1a1SMauro Carvalho Chehab #define IA_CSS_COPYSINK_SEM_INDEX 0
599d4fa1a1SMauro Carvalho Chehab #define IA_CSS_TAGGER_SEM_INDEX 1
609d4fa1a1SMauro Carvalho Chehab
619d4fa1a1SMauro Carvalho Chehab /* Force generation of output event. Used by acceleration pipe. */
629d4fa1a1SMauro Carvalho Chehab #define IA_CSS_POST_OUT_EVENT_FORCE 2
639d4fa1a1SMauro Carvalho Chehab
649d4fa1a1SMauro Carvalho Chehab #define SH_CSS_MAX_BINARY_NAME 64
659d4fa1a1SMauro Carvalho Chehab
669d4fa1a1SMauro Carvalho Chehab #define SP_DEBUG_NONE (0)
679d4fa1a1SMauro Carvalho Chehab #define SP_DEBUG_DUMP (1)
689d4fa1a1SMauro Carvalho Chehab #define SP_DEBUG_COPY (2)
699d4fa1a1SMauro Carvalho Chehab #define SP_DEBUG_TRACE (3)
709d4fa1a1SMauro Carvalho Chehab #define SP_DEBUG_MINIMAL (4)
719d4fa1a1SMauro Carvalho Chehab
729d4fa1a1SMauro Carvalho Chehab #define SP_DEBUG SP_DEBUG_NONE
739d4fa1a1SMauro Carvalho Chehab #define SP_DEBUG_MINIMAL_OVERWRITE 1
749d4fa1a1SMauro Carvalho Chehab
759d4fa1a1SMauro Carvalho Chehab #define SH_CSS_TNR_BIT_DEPTH 8
769d4fa1a1SMauro Carvalho Chehab #define SH_CSS_REF_BIT_DEPTH 8
779d4fa1a1SMauro Carvalho Chehab
789d4fa1a1SMauro Carvalho Chehab /* keep next up to date with the definition for MAX_CB_ELEMS_FOR_TAGGER in tagger.sp.c */
799d4fa1a1SMauro Carvalho Chehab #define NUM_CONTINUOUS_FRAMES 15
809d4fa1a1SMauro Carvalho Chehab #define NUM_MIPI_FRAMES_PER_STREAM 2
819d4fa1a1SMauro Carvalho Chehab
829d4fa1a1SMauro Carvalho Chehab #define NUM_ONLINE_INIT_CONTINUOUS_FRAMES 2
839d4fa1a1SMauro Carvalho Chehab
849d4fa1a1SMauro Carvalho Chehab #define NR_OF_PIPELINES IA_CSS_PIPE_ID_NUM /* Must match with IA_CSS_PIPE_ID_NUM */
859d4fa1a1SMauro Carvalho Chehab
869d4fa1a1SMauro Carvalho Chehab #define SH_CSS_MAX_IF_CONFIGS 3 /* Must match with IA_CSS_NR_OF_CONFIGS (not defined yet).*/
879d4fa1a1SMauro Carvalho Chehab #define SH_CSS_IF_CONFIG_NOT_NEEDED 0xFF
889d4fa1a1SMauro Carvalho Chehab
899d4fa1a1SMauro Carvalho Chehab /*
909d4fa1a1SMauro Carvalho Chehab * SH_CSS_MAX_SP_THREADS:
919d4fa1a1SMauro Carvalho Chehab * sp threads visible to host with connected communication queues
929d4fa1a1SMauro Carvalho Chehab * these threads are capable of running an image pipe
939d4fa1a1SMauro Carvalho Chehab * SH_CSS_MAX_SP_INTERNAL_THREADS:
949d4fa1a1SMauro Carvalho Chehab * internal sp service threads, no communication queues to host
959d4fa1a1SMauro Carvalho Chehab * these threads can't be used as image pipe
969d4fa1a1SMauro Carvalho Chehab */
979d4fa1a1SMauro Carvalho Chehab
989e22032eSMauro Carvalho Chehab #if !defined(ISP2401)
999d4fa1a1SMauro Carvalho Chehab #define SH_CSS_SP_INTERNAL_METADATA_THREAD 1
1009d4fa1a1SMauro Carvalho Chehab #else
1019d4fa1a1SMauro Carvalho Chehab #define SH_CSS_SP_INTERNAL_METADATA_THREAD 0
1029d4fa1a1SMauro Carvalho Chehab #endif
1039d4fa1a1SMauro Carvalho Chehab
1049d4fa1a1SMauro Carvalho Chehab #define SH_CSS_SP_INTERNAL_SERVICE_THREAD 1
1059d4fa1a1SMauro Carvalho Chehab
1069d4fa1a1SMauro Carvalho Chehab #define SH_CSS_MAX_SP_THREADS 5
1079d4fa1a1SMauro Carvalho Chehab
1089d4fa1a1SMauro Carvalho Chehab #define SH_CSS_MAX_SP_INTERNAL_THREADS (\
1099d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_INTERNAL_SERVICE_THREAD +\
1109d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_INTERNAL_METADATA_THREAD)
1119d4fa1a1SMauro Carvalho Chehab
1129d4fa1a1SMauro Carvalho Chehab #define SH_CSS_MAX_PIPELINES SH_CSS_MAX_SP_THREADS
1139d4fa1a1SMauro Carvalho Chehab
1149d4fa1a1SMauro Carvalho Chehab /**
1159d4fa1a1SMauro Carvalho Chehab * The C99 standard does not specify the exact object representation of structs;
1169d4fa1a1SMauro Carvalho Chehab * the representation is compiler dependent.
1179d4fa1a1SMauro Carvalho Chehab *
1189d4fa1a1SMauro Carvalho Chehab * The structs that are communicated between host and SP/ISP should have the
1199d4fa1a1SMauro Carvalho Chehab * exact same object representation. The compiler that is used to compile the
1209d4fa1a1SMauro Carvalho Chehab * firmware is hivecc.
1219d4fa1a1SMauro Carvalho Chehab *
1229d4fa1a1SMauro Carvalho Chehab * To check if a different compiler, used to compile a host application, uses
1239d4fa1a1SMauro Carvalho Chehab * another object representation, macros are defined specifying the size of
1249d4fa1a1SMauro Carvalho Chehab * the structs as expected by the firmware.
1259d4fa1a1SMauro Carvalho Chehab *
1269d4fa1a1SMauro Carvalho Chehab * A host application shall verify that a sizeof( ) of the struct is equal to
1279d4fa1a1SMauro Carvalho Chehab * the SIZE_OF_XXX macro of the corresponding struct. If they are not
1289d4fa1a1SMauro Carvalho Chehab * equal, functionality will break.
1299d4fa1a1SMauro Carvalho Chehab */
1309d4fa1a1SMauro Carvalho Chehab #define CALC_ALIGNMENT_MEMBER(x, y) (CEIL_MUL(x, y) - x)
1319d4fa1a1SMauro Carvalho Chehab #define SIZE_OF_HRT_VADDRESS sizeof(hive_uint32)
1329d4fa1a1SMauro Carvalho Chehab #define SIZE_OF_IA_CSS_PTR sizeof(uint32_t)
1339d4fa1a1SMauro Carvalho Chehab
1349d4fa1a1SMauro Carvalho Chehab /* Number of SP's */
1359d4fa1a1SMauro Carvalho Chehab #define NUM_OF_SPS 1
1369d4fa1a1SMauro Carvalho Chehab
1379d4fa1a1SMauro Carvalho Chehab #define NUM_OF_BLS 0
1389d4fa1a1SMauro Carvalho Chehab
1399d4fa1a1SMauro Carvalho Chehab /* Enum for order of Binaries */
1409d4fa1a1SMauro Carvalho Chehab enum sh_css_order_binaries {
1419d4fa1a1SMauro Carvalho Chehab SP_FIRMWARE = 0,
1429d4fa1a1SMauro Carvalho Chehab ISP_FIRMWARE
1439d4fa1a1SMauro Carvalho Chehab };
1449d4fa1a1SMauro Carvalho Chehab
1459d4fa1a1SMauro Carvalho Chehab /*
1469d4fa1a1SMauro Carvalho Chehab * JB: keep next enum in sync with thread id's
1479d4fa1a1SMauro Carvalho Chehab * and pipe id's
1489d4fa1a1SMauro Carvalho Chehab */
1499d4fa1a1SMauro Carvalho Chehab enum sh_css_pipe_config_override {
1509d4fa1a1SMauro Carvalho Chehab SH_CSS_PIPE_CONFIG_OVRD_NONE = 0,
1519d4fa1a1SMauro Carvalho Chehab SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD = 0xffff
1529d4fa1a1SMauro Carvalho Chehab };
1539d4fa1a1SMauro Carvalho Chehab
1549d4fa1a1SMauro Carvalho Chehab enum host2sp_commands {
1559d4fa1a1SMauro Carvalho Chehab host2sp_cmd_error = 0,
1569d4fa1a1SMauro Carvalho Chehab /*
1579d4fa1a1SMauro Carvalho Chehab * The host2sp_cmd_ready command is the only command written by the SP
1589d4fa1a1SMauro Carvalho Chehab * It acknowledges that is previous command has been received.
1599d4fa1a1SMauro Carvalho Chehab * (this does not mean that the command has been executed)
1609d4fa1a1SMauro Carvalho Chehab * It also indicates that a new command can be send (it is a queue
1619d4fa1a1SMauro Carvalho Chehab * with depth 1).
1629d4fa1a1SMauro Carvalho Chehab */
1639d4fa1a1SMauro Carvalho Chehab host2sp_cmd_ready = 1,
1649d4fa1a1SMauro Carvalho Chehab /* Command written by the Host */
1659d4fa1a1SMauro Carvalho Chehab host2sp_cmd_dummy, /* No action, can be used as watchdog */
1669d4fa1a1SMauro Carvalho Chehab host2sp_cmd_start_flash, /* Request SP to start the flash */
1679d4fa1a1SMauro Carvalho Chehab host2sp_cmd_terminate, /* SP should terminate itself */
1689d4fa1a1SMauro Carvalho Chehab N_host2sp_cmd
1699d4fa1a1SMauro Carvalho Chehab };
1709d4fa1a1SMauro Carvalho Chehab
1719d4fa1a1SMauro Carvalho Chehab /* Enumeration used to indicate the events that are produced by
1729d4fa1a1SMauro Carvalho Chehab * the SP and consumed by the Host.
1739d4fa1a1SMauro Carvalho Chehab *
1749d4fa1a1SMauro Carvalho Chehab * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC:
1759d4fa1a1SMauro Carvalho Chehab * 1) "enum ia_css_event_type" (ia_css_event_public.h)
1769d4fa1a1SMauro Carvalho Chehab * 2) "enum sh_css_sp_event_type" (sh_css_internal.h)
1779d4fa1a1SMauro Carvalho Chehab * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c)
1789d4fa1a1SMauro Carvalho Chehab * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c)
1799d4fa1a1SMauro Carvalho Chehab */
1809d4fa1a1SMauro Carvalho Chehab enum sh_css_sp_event_type {
1819d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_OUTPUT_FRAME_DONE,
1829d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_SECOND_OUTPUT_FRAME_DONE,
1839d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_VF_OUTPUT_FRAME_DONE,
1849d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_SECOND_VF_OUTPUT_FRAME_DONE,
1859d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_3A_STATISTICS_DONE,
1869d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_DIS_STATISTICS_DONE,
1879d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_PIPELINE_DONE,
1889d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_FRAME_TAGGED,
1899d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_INPUT_FRAME_DONE,
1909d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_METADATA_DONE,
1919d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_LACE_STATISTICS_DONE,
1929d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_ACC_STAGE_COMPLETE,
1939d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_TIMER,
1949d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_PORT_EOF,
1959d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_FW_WARNING,
1969d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_FW_ASSERT,
1979d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_EVENT_NR_OF_TYPES /* must be last */
1989d4fa1a1SMauro Carvalho Chehab };
1999d4fa1a1SMauro Carvalho Chehab
2009d4fa1a1SMauro Carvalho Chehab /* xmem address map allocation per pipeline, css pointers */
201100e8989SMauro Carvalho Chehab /* Note that the struct below should only consist of ia_css_ptr-es
2029d4fa1a1SMauro Carvalho Chehab Otherwise this will cause a fail in the function ref_sh_css_ddr_address_map
2039d4fa1a1SMauro Carvalho Chehab */
2049d4fa1a1SMauro Carvalho Chehab struct sh_css_ddr_address_map {
205100e8989SMauro Carvalho Chehab ia_css_ptr isp_param;
206100e8989SMauro Carvalho Chehab ia_css_ptr isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES];
207100e8989SMauro Carvalho Chehab ia_css_ptr macc_tbl;
208100e8989SMauro Carvalho Chehab ia_css_ptr fpn_tbl;
209100e8989SMauro Carvalho Chehab ia_css_ptr sc_tbl;
210100e8989SMauro Carvalho Chehab ia_css_ptr tetra_r_x;
211100e8989SMauro Carvalho Chehab ia_css_ptr tetra_r_y;
212100e8989SMauro Carvalho Chehab ia_css_ptr tetra_gr_x;
213100e8989SMauro Carvalho Chehab ia_css_ptr tetra_gr_y;
214100e8989SMauro Carvalho Chehab ia_css_ptr tetra_gb_x;
215100e8989SMauro Carvalho Chehab ia_css_ptr tetra_gb_y;
216100e8989SMauro Carvalho Chehab ia_css_ptr tetra_b_x;
217100e8989SMauro Carvalho Chehab ia_css_ptr tetra_b_y;
218100e8989SMauro Carvalho Chehab ia_css_ptr tetra_ratb_x;
219100e8989SMauro Carvalho Chehab ia_css_ptr tetra_ratb_y;
220100e8989SMauro Carvalho Chehab ia_css_ptr tetra_batr_x;
221100e8989SMauro Carvalho Chehab ia_css_ptr tetra_batr_y;
222100e8989SMauro Carvalho Chehab ia_css_ptr dvs_6axis_params_y;
2239d4fa1a1SMauro Carvalho Chehab };
2249d4fa1a1SMauro Carvalho Chehab
2259d4fa1a1SMauro Carvalho Chehab #define SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT \
2269d4fa1a1SMauro Carvalho Chehab (SIZE_OF_HRT_VADDRESS + \
2279d4fa1a1SMauro Carvalho Chehab (SH_CSS_MAX_STAGES * IA_CSS_NUM_MEMORIES * SIZE_OF_HRT_VADDRESS) + \
2289d4fa1a1SMauro Carvalho Chehab (16 * SIZE_OF_HRT_VADDRESS))
2299d4fa1a1SMauro Carvalho Chehab
2309d4fa1a1SMauro Carvalho Chehab /* xmem address map allocation per pipeline */
2319d4fa1a1SMauro Carvalho Chehab struct sh_css_ddr_address_map_size {
2329d4fa1a1SMauro Carvalho Chehab size_t isp_param;
2339d4fa1a1SMauro Carvalho Chehab size_t isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES];
2349d4fa1a1SMauro Carvalho Chehab size_t macc_tbl;
2359d4fa1a1SMauro Carvalho Chehab size_t fpn_tbl;
2369d4fa1a1SMauro Carvalho Chehab size_t sc_tbl;
2379d4fa1a1SMauro Carvalho Chehab size_t tetra_r_x;
2389d4fa1a1SMauro Carvalho Chehab size_t tetra_r_y;
2399d4fa1a1SMauro Carvalho Chehab size_t tetra_gr_x;
2409d4fa1a1SMauro Carvalho Chehab size_t tetra_gr_y;
2419d4fa1a1SMauro Carvalho Chehab size_t tetra_gb_x;
2429d4fa1a1SMauro Carvalho Chehab size_t tetra_gb_y;
2439d4fa1a1SMauro Carvalho Chehab size_t tetra_b_x;
2449d4fa1a1SMauro Carvalho Chehab size_t tetra_b_y;
2459d4fa1a1SMauro Carvalho Chehab size_t tetra_ratb_x;
2469d4fa1a1SMauro Carvalho Chehab size_t tetra_ratb_y;
2479d4fa1a1SMauro Carvalho Chehab size_t tetra_batr_x;
2489d4fa1a1SMauro Carvalho Chehab size_t tetra_batr_y;
2499d4fa1a1SMauro Carvalho Chehab size_t dvs_6axis_params_y;
2509d4fa1a1SMauro Carvalho Chehab };
2519d4fa1a1SMauro Carvalho Chehab
2529d4fa1a1SMauro Carvalho Chehab struct sh_css_ddr_address_map_compound {
2539d4fa1a1SMauro Carvalho Chehab struct sh_css_ddr_address_map map;
2549d4fa1a1SMauro Carvalho Chehab struct sh_css_ddr_address_map_size size;
2559d4fa1a1SMauro Carvalho Chehab };
2569d4fa1a1SMauro Carvalho Chehab
2579d4fa1a1SMauro Carvalho Chehab struct ia_css_isp_parameter_set_info {
2589d4fa1a1SMauro Carvalho Chehab struct sh_css_ddr_address_map
2599d4fa1a1SMauro Carvalho Chehab mem_map;/** pointers to Parameters in ISP format IMPT:
2609d4fa1a1SMauro Carvalho Chehab This should be first member of this struct */
2619d4fa1a1SMauro Carvalho Chehab u32
2629d4fa1a1SMauro Carvalho Chehab isp_parameters_id;/** Unique ID to track which config was actually applied to a particular frame */
2639d4fa1a1SMauro Carvalho Chehab ia_css_ptr
2649d4fa1a1SMauro Carvalho Chehab output_frame_ptr;/** Output frame to which this config has to be applied (optional) */
2659d4fa1a1SMauro Carvalho Chehab };
2669d4fa1a1SMauro Carvalho Chehab
2679d4fa1a1SMauro Carvalho Chehab /* this struct contains all arguments that can be passed to
2689d4fa1a1SMauro Carvalho Chehab a binary. It depends on the binary which ones are used. */
2699d4fa1a1SMauro Carvalho Chehab struct sh_css_binary_args {
2709d4fa1a1SMauro Carvalho Chehab struct ia_css_frame *in_frame; /* input frame */
271f6117977SMauro Carvalho Chehab const struct ia_css_frame
2729d4fa1a1SMauro Carvalho Chehab *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; /* reference input frame */
273*83946783SMauro Carvalho Chehab const struct ia_css_frame *tnr_frames[NUM_VIDEO_TNR_FRAMES]; /* tnr frames */
2749d4fa1a1SMauro Carvalho Chehab struct ia_css_frame
2759d4fa1a1SMauro Carvalho Chehab *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; /* output frame */
2769d4fa1a1SMauro Carvalho Chehab struct ia_css_frame *out_vf_frame; /* viewfinder output frame */
2779d4fa1a1SMauro Carvalho Chehab bool copy_vf;
2789d4fa1a1SMauro Carvalho Chehab bool copy_output;
2799d4fa1a1SMauro Carvalho Chehab unsigned int vf_downscale_log2;
2809d4fa1a1SMauro Carvalho Chehab };
2819d4fa1a1SMauro Carvalho Chehab
2829d4fa1a1SMauro Carvalho Chehab #if SP_DEBUG == SP_DEBUG_DUMP
2839d4fa1a1SMauro Carvalho Chehab
2849d4fa1a1SMauro Carvalho Chehab #define SH_CSS_NUM_SP_DEBUG 48
2859d4fa1a1SMauro Carvalho Chehab
2869d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_debug_state {
2879d4fa1a1SMauro Carvalho Chehab unsigned int error;
2889d4fa1a1SMauro Carvalho Chehab unsigned int debug[SH_CSS_NUM_SP_DEBUG];
2899d4fa1a1SMauro Carvalho Chehab };
2909d4fa1a1SMauro Carvalho Chehab
2919d4fa1a1SMauro Carvalho Chehab #elif SP_DEBUG == SP_DEBUG_COPY
2929d4fa1a1SMauro Carvalho Chehab
2939d4fa1a1SMauro Carvalho Chehab #define SH_CSS_SP_DBG_TRACE_DEPTH (40)
2949d4fa1a1SMauro Carvalho Chehab
2959d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_debug_trace {
2969d4fa1a1SMauro Carvalho Chehab u16 frame;
2979d4fa1a1SMauro Carvalho Chehab u16 line;
2989d4fa1a1SMauro Carvalho Chehab u16 pixel_distance;
2999d4fa1a1SMauro Carvalho Chehab u16 mipi_used_dword;
3009d4fa1a1SMauro Carvalho Chehab u16 sp_index;
3019d4fa1a1SMauro Carvalho Chehab };
3029d4fa1a1SMauro Carvalho Chehab
3039d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_debug_state {
3049d4fa1a1SMauro Carvalho Chehab u16 if_start_line;
3059d4fa1a1SMauro Carvalho Chehab u16 if_start_column;
3069d4fa1a1SMauro Carvalho Chehab u16 if_cropped_height;
3079d4fa1a1SMauro Carvalho Chehab u16 if_cropped_width;
3089d4fa1a1SMauro Carvalho Chehab unsigned int index;
3099d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_debug_trace
3109d4fa1a1SMauro Carvalho Chehab trace[SH_CSS_SP_DBG_TRACE_DEPTH];
3119d4fa1a1SMauro Carvalho Chehab };
3129d4fa1a1SMauro Carvalho Chehab
3139d4fa1a1SMauro Carvalho Chehab #elif SP_DEBUG == SP_DEBUG_TRACE
3149d4fa1a1SMauro Carvalho Chehab
3159d4fa1a1SMauro Carvalho Chehab /* Example of just one global trace */
3169d4fa1a1SMauro Carvalho Chehab #define SH_CSS_SP_DBG_NR_OF_TRACES (1)
3179d4fa1a1SMauro Carvalho Chehab #define SH_CSS_SP_DBG_TRACE_DEPTH (40)
3189d4fa1a1SMauro Carvalho Chehab
3199d4fa1a1SMauro Carvalho Chehab #define SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS (13)
3209d4fa1a1SMauro Carvalho Chehab
3219d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_debug_trace {
3229d4fa1a1SMauro Carvalho Chehab u16 time_stamp;
3239d4fa1a1SMauro Carvalho Chehab u16 location; /* bit 15..13 = file_id, 12..0 = line nr. */
3249d4fa1a1SMauro Carvalho Chehab u32 data;
3259d4fa1a1SMauro Carvalho Chehab };
3269d4fa1a1SMauro Carvalho Chehab
3279d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_debug_state {
3289d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_debug_trace
3299d4fa1a1SMauro Carvalho Chehab trace[SH_CSS_SP_DBG_NR_OF_TRACES][SH_CSS_SP_DBG_TRACE_DEPTH];
3309d4fa1a1SMauro Carvalho Chehab u16 index_last[SH_CSS_SP_DBG_NR_OF_TRACES];
3319d4fa1a1SMauro Carvalho Chehab u8 index[SH_CSS_SP_DBG_NR_OF_TRACES];
3329d4fa1a1SMauro Carvalho Chehab };
3339d4fa1a1SMauro Carvalho Chehab
3349d4fa1a1SMauro Carvalho Chehab #elif SP_DEBUG == SP_DEBUG_MINIMAL
3359d4fa1a1SMauro Carvalho Chehab
3369d4fa1a1SMauro Carvalho Chehab #define SH_CSS_NUM_SP_DEBUG 128
3379d4fa1a1SMauro Carvalho Chehab
3389d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_debug_state {
3399d4fa1a1SMauro Carvalho Chehab unsigned int error;
3409d4fa1a1SMauro Carvalho Chehab unsigned int debug[SH_CSS_NUM_SP_DEBUG];
3419d4fa1a1SMauro Carvalho Chehab };
3429d4fa1a1SMauro Carvalho Chehab
3439d4fa1a1SMauro Carvalho Chehab #endif
3449d4fa1a1SMauro Carvalho Chehab
3459d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_debug_command {
3469d4fa1a1SMauro Carvalho Chehab /*
3479d4fa1a1SMauro Carvalho Chehab * The DMA software-mask,
3489d4fa1a1SMauro Carvalho Chehab * Bit 31...24: unused.
3499d4fa1a1SMauro Carvalho Chehab * Bit 23...16: unused.
3509d4fa1a1SMauro Carvalho Chehab * Bit 15...08: reading-request enabling bits for DMA channel 7..0
3519d4fa1a1SMauro Carvalho Chehab * Bit 07...00: writing-request enabling bits for DMA channel 7..0
3529d4fa1a1SMauro Carvalho Chehab *
3539d4fa1a1SMauro Carvalho Chehab * For example, "0...0 0...0 11111011 11111101" indicates that the
3549d4fa1a1SMauro Carvalho Chehab * writing request through DMA Channel 1 and the reading request
3559d4fa1a1SMauro Carvalho Chehab * through DMA channel 2 are both disabled. The others are enabled.
3569d4fa1a1SMauro Carvalho Chehab */
3579d4fa1a1SMauro Carvalho Chehab u32 dma_sw_reg;
3589d4fa1a1SMauro Carvalho Chehab };
3599d4fa1a1SMauro Carvalho Chehab
360641c2292SMauro Carvalho Chehab #if !defined(ISP2401)
3619d4fa1a1SMauro Carvalho Chehab /* SP input formatter configuration.*/
3629d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_input_formatter_set {
3639d4fa1a1SMauro Carvalho Chehab u32 stream_format;
3649d4fa1a1SMauro Carvalho Chehab input_formatter_cfg_t config_a;
3659d4fa1a1SMauro Carvalho Chehab input_formatter_cfg_t config_b;
3669d4fa1a1SMauro Carvalho Chehab };
3679d4fa1a1SMauro Carvalho Chehab #endif
3689d4fa1a1SMauro Carvalho Chehab
3699d4fa1a1SMauro Carvalho Chehab #define IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT (3)
3709d4fa1a1SMauro Carvalho Chehab
3719d4fa1a1SMauro Carvalho Chehab /* SP configuration information */
3729d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_config {
3739d4fa1a1SMauro Carvalho Chehab u8 no_isp_sync; /* Signal host immediately after start */
3749d4fa1a1SMauro Carvalho Chehab u8 enable_raw_pool_locking; /** Enable Raw Buffer Locking for HALv3 Support */
3759d4fa1a1SMauro Carvalho Chehab u8 lock_all;
3769d4fa1a1SMauro Carvalho Chehab /** If raw buffer locking is enabled, this flag indicates whether raw
3779d4fa1a1SMauro Carvalho Chehab frames are locked when their EOF event is successfully sent to the
3789d4fa1a1SMauro Carvalho Chehab host (true) or when they are passed to the preview/video pipe
3799d4fa1a1SMauro Carvalho Chehab (false). */
380641c2292SMauro Carvalho Chehab #if !defined(ISP2401)
3819d4fa1a1SMauro Carvalho Chehab struct {
3829d4fa1a1SMauro Carvalho Chehab u8 a_changed;
3839d4fa1a1SMauro Carvalho Chehab u8 b_changed;
3849d4fa1a1SMauro Carvalho Chehab u8 isp_2ppc;
3859d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_input_formatter_set
3869d4fa1a1SMauro Carvalho Chehab set[SH_CSS_MAX_IF_CONFIGS]; /* CSI-2 port is used as index. */
3879d4fa1a1SMauro Carvalho Chehab } input_formatter;
3889d4fa1a1SMauro Carvalho Chehab #endif
389641c2292SMauro Carvalho Chehab #if !defined(ISP2401)
3909d4fa1a1SMauro Carvalho Chehab sync_generator_cfg_t sync_gen;
3919d4fa1a1SMauro Carvalho Chehab tpg_cfg_t tpg;
3929d4fa1a1SMauro Carvalho Chehab prbs_cfg_t prbs;
3939d4fa1a1SMauro Carvalho Chehab input_system_cfg_t input_circuit;
3949d4fa1a1SMauro Carvalho Chehab u8 input_circuit_cfg_changed;
3959d4fa1a1SMauro Carvalho Chehab u32 mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT];
3969d4fa1a1SMauro Carvalho Chehab #endif
3979d4fa1a1SMauro Carvalho Chehab u8 enable_isys_event_queue;
3989d4fa1a1SMauro Carvalho Chehab u8 disable_cont_vf;
3999d4fa1a1SMauro Carvalho Chehab };
4009d4fa1a1SMauro Carvalho Chehab
4019d4fa1a1SMauro Carvalho Chehab enum sh_css_stage_type {
4029d4fa1a1SMauro Carvalho Chehab SH_CSS_SP_STAGE_TYPE = 0,
4039d4fa1a1SMauro Carvalho Chehab SH_CSS_ISP_STAGE_TYPE = 1
4049d4fa1a1SMauro Carvalho Chehab };
4059d4fa1a1SMauro Carvalho Chehab
4069d4fa1a1SMauro Carvalho Chehab #define SH_CSS_NUM_STAGE_TYPES 2
4079d4fa1a1SMauro Carvalho Chehab
4089d4fa1a1SMauro Carvalho Chehab #define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS BIT(0)
4099d4fa1a1SMauro Carvalho Chehab #define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS_MASK \
4109d4fa1a1SMauro Carvalho Chehab ((SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << SH_CSS_MAX_SP_THREADS) - 1)
4119d4fa1a1SMauro Carvalho Chehab
412641c2292SMauro Carvalho Chehab #if defined(ISP2401)
4139d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_pipeline_terminal {
4149d4fa1a1SMauro Carvalho Chehab union {
4159d4fa1a1SMauro Carvalho Chehab /* Input System 2401 */
4169d4fa1a1SMauro Carvalho Chehab virtual_input_system_stream_t
4179d4fa1a1SMauro Carvalho Chehab virtual_input_system_stream[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH];
4189d4fa1a1SMauro Carvalho Chehab } context;
4199d4fa1a1SMauro Carvalho Chehab /*
4209d4fa1a1SMauro Carvalho Chehab * TODO
4219d4fa1a1SMauro Carvalho Chehab * - Remove "virtual_input_system_cfg" when the ISYS2401 DLI is ready.
4229d4fa1a1SMauro Carvalho Chehab */
4239d4fa1a1SMauro Carvalho Chehab union {
4249d4fa1a1SMauro Carvalho Chehab /* Input System 2401 */
4259d4fa1a1SMauro Carvalho Chehab virtual_input_system_stream_cfg_t
4269d4fa1a1SMauro Carvalho Chehab virtual_input_system_stream_cfg[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH];
4279d4fa1a1SMauro Carvalho Chehab } ctrl;
4289d4fa1a1SMauro Carvalho Chehab };
4299d4fa1a1SMauro Carvalho Chehab
4309d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_pipeline_io {
4319d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_pipeline_terminal input;
4329d4fa1a1SMauro Carvalho Chehab /* pqiao: comment out temporarily to save dmem */
4339d4fa1a1SMauro Carvalho Chehab /*struct sh_css_sp_pipeline_terminal output;*/
4349d4fa1a1SMauro Carvalho Chehab };
4359d4fa1a1SMauro Carvalho Chehab
4369d4fa1a1SMauro Carvalho Chehab /* This struct tracks how many streams are registered per CSI port.
4379d4fa1a1SMauro Carvalho Chehab * This is used to track which streams have already been configured.
4389d4fa1a1SMauro Carvalho Chehab * Only when all streams are configured, the CSI RX is started for that port.
4399d4fa1a1SMauro Carvalho Chehab */
4409d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_pipeline_io_status {
4419d4fa1a1SMauro Carvalho Chehab u32 active[N_INPUT_SYSTEM_CSI_PORT]; /** registered streams */
4429d4fa1a1SMauro Carvalho Chehab u32 running[N_INPUT_SYSTEM_CSI_PORT]; /** configured streams */
4439d4fa1a1SMauro Carvalho Chehab };
4449d4fa1a1SMauro Carvalho Chehab
4459d4fa1a1SMauro Carvalho Chehab #endif
4469d4fa1a1SMauro Carvalho Chehab enum sh_css_port_dir {
4479d4fa1a1SMauro Carvalho Chehab SH_CSS_PORT_INPUT = 0,
4489d4fa1a1SMauro Carvalho Chehab SH_CSS_PORT_OUTPUT = 1
4499d4fa1a1SMauro Carvalho Chehab };
4509d4fa1a1SMauro Carvalho Chehab
4519d4fa1a1SMauro Carvalho Chehab enum sh_css_port_type {
4529d4fa1a1SMauro Carvalho Chehab SH_CSS_HOST_TYPE = 0,
4539d4fa1a1SMauro Carvalho Chehab SH_CSS_COPYSINK_TYPE = 1,
4549d4fa1a1SMauro Carvalho Chehab SH_CSS_TAGGERSINK_TYPE = 2
4559d4fa1a1SMauro Carvalho Chehab };
4569d4fa1a1SMauro Carvalho Chehab
4579d4fa1a1SMauro Carvalho Chehab /* Pipe inout settings: output port on 7-4bits, input port on 3-0bits */
4589d4fa1a1SMauro Carvalho Chehab #define SH_CSS_PORT_FLD_WIDTH_IN_BITS (4)
4599d4fa1a1SMauro Carvalho Chehab #define SH_CSS_PORT_TYPE_BIT_FLD(pt) (0x1 << (pt))
4609d4fa1a1SMauro Carvalho Chehab #define SH_CSS_PORT_FLD(pd) ((pd) ? SH_CSS_PORT_FLD_WIDTH_IN_BITS : 0)
4619d4fa1a1SMauro Carvalho Chehab #define SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) ((p) |= (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd)))
4629d4fa1a1SMauro Carvalho Chehab #define SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt) ((p) &= ~(SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd)))
4639d4fa1a1SMauro Carvalho Chehab #define SH_CSS_PIPE_PORT_CONFIG_SET(p, pd, pt, val) ((val) ? \
4649d4fa1a1SMauro Carvalho Chehab SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) : SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt))
4659d4fa1a1SMauro Carvalho Chehab #define SH_CSS_PIPE_PORT_CONFIG_GET(p, pd, pt) ((p) & (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd)))
4669d4fa1a1SMauro Carvalho Chehab #define SH_CSS_PIPE_PORT_CONFIG_IS_CONTINUOUS(p) \
4679d4fa1a1SMauro Carvalho Chehab (!(SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_INPUT, SH_CSS_HOST_TYPE) && \
4689d4fa1a1SMauro Carvalho Chehab SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_OUTPUT, SH_CSS_HOST_TYPE)))
4699d4fa1a1SMauro Carvalho Chehab
4709d4fa1a1SMauro Carvalho Chehab #define IA_CSS_ACQUIRE_ISP_POS 31
4719d4fa1a1SMauro Carvalho Chehab
4729d4fa1a1SMauro Carvalho Chehab /* Flags for metadata processing */
4739d4fa1a1SMauro Carvalho Chehab #define SH_CSS_METADATA_ENABLED 0x01
4749d4fa1a1SMauro Carvalho Chehab #define SH_CSS_METADATA_PROCESSED 0x02
4759d4fa1a1SMauro Carvalho Chehab #define SH_CSS_METADATA_OFFLINE_MODE 0x04
4769d4fa1a1SMauro Carvalho Chehab #define SH_CSS_METADATA_WAIT_INPUT 0x08
4779d4fa1a1SMauro Carvalho Chehab
4789d4fa1a1SMauro Carvalho Chehab /* @brief Free an array of metadata buffers.
4799d4fa1a1SMauro Carvalho Chehab *
4809d4fa1a1SMauro Carvalho Chehab * @param[in] num_bufs Number of metadata buffers to be freed.
4819d4fa1a1SMauro Carvalho Chehab * @param[in] bufs Pointer of array of metadata buffers.
4829d4fa1a1SMauro Carvalho Chehab *
4839d4fa1a1SMauro Carvalho Chehab * This function frees an array of metadata buffers.
4849d4fa1a1SMauro Carvalho Chehab */
4859d4fa1a1SMauro Carvalho Chehab void
4869d4fa1a1SMauro Carvalho Chehab ia_css_metadata_free_multiple(unsigned int num_bufs,
4879d4fa1a1SMauro Carvalho Chehab struct ia_css_metadata **bufs);
4889d4fa1a1SMauro Carvalho Chehab
4899d4fa1a1SMauro Carvalho Chehab /* Macro for handling pipe_qos_config */
4909d4fa1a1SMauro Carvalho Chehab #define QOS_INVALID (~0U)
4919d4fa1a1SMauro Carvalho Chehab
4929d4fa1a1SMauro Carvalho Chehab /* Information for a pipeline */
4939d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_pipeline {
4949d4fa1a1SMauro Carvalho Chehab u32 pipe_id; /* the pipe ID */
4959d4fa1a1SMauro Carvalho Chehab u32 pipe_num; /* the dynamic pipe number */
4969d4fa1a1SMauro Carvalho Chehab u32 thread_id; /* the sp thread ID */
4979d4fa1a1SMauro Carvalho Chehab u32 pipe_config; /* the pipe config */
4989d4fa1a1SMauro Carvalho Chehab u32 pipe_qos_config; /* Bitmap of multiple QOS extension fw state.
4999d4fa1a1SMauro Carvalho Chehab (0xFFFFFFFF) indicates non QOS pipe.*/
5009d4fa1a1SMauro Carvalho Chehab u32 inout_port_config;
5019d4fa1a1SMauro Carvalho Chehab u32 required_bds_factor;
5029d4fa1a1SMauro Carvalho Chehab u32 dvs_frame_delay;
5039d4fa1a1SMauro Carvalho Chehab u32 input_system_mode; /* enum ia_css_input_mode */
5049d4fa1a1SMauro Carvalho Chehab u32 port_id; /* port_id for input system */
5059d4fa1a1SMauro Carvalho Chehab u32 num_stages; /* the pipe config */
5069d4fa1a1SMauro Carvalho Chehab u32 running; /* needed for pipe termination */
507100e8989SMauro Carvalho Chehab ia_css_ptr sp_stage_addr[SH_CSS_MAX_STAGES];
508100e8989SMauro Carvalho Chehab ia_css_ptr scaler_pp_lut; /* Early bound LUT */
5099d4fa1a1SMauro Carvalho Chehab u32 dummy; /* stage ptr is only used on sp but lives in
5109d4fa1a1SMauro Carvalho Chehab this struct; needs cleanup */
5119d4fa1a1SMauro Carvalho Chehab s32 num_execs; /* number of times to run if this is
5129d4fa1a1SMauro Carvalho Chehab an acceleration pipe. */
5139d4fa1a1SMauro Carvalho Chehab struct {
5149d4fa1a1SMauro Carvalho Chehab u32 format; /* Metadata format in hrt format */
5159d4fa1a1SMauro Carvalho Chehab u32 width; /* Width of a line */
5169d4fa1a1SMauro Carvalho Chehab u32 height; /* Number of lines */
5179d4fa1a1SMauro Carvalho Chehab u32 stride; /* Stride (in bytes) per line */
5189d4fa1a1SMauro Carvalho Chehab u32 size; /* Total size (in bytes) */
519100e8989SMauro Carvalho Chehab ia_css_ptr cont_buf; /* Address of continuous buffer */
5209d4fa1a1SMauro Carvalho Chehab } metadata;
5219d4fa1a1SMauro Carvalho Chehab u32 output_frame_queue_id;
5229d4fa1a1SMauro Carvalho Chehab union {
5239d4fa1a1SMauro Carvalho Chehab struct {
5249d4fa1a1SMauro Carvalho Chehab u32 bytes_available;
5259d4fa1a1SMauro Carvalho Chehab } bin;
5269d4fa1a1SMauro Carvalho Chehab struct {
5279d4fa1a1SMauro Carvalho Chehab u32 height;
5289d4fa1a1SMauro Carvalho Chehab u32 width;
5299d4fa1a1SMauro Carvalho Chehab u32 padded_width;
5309d4fa1a1SMauro Carvalho Chehab u32 max_input_width;
5319d4fa1a1SMauro Carvalho Chehab u32 raw_bit_depth;
5329d4fa1a1SMauro Carvalho Chehab } raw;
5339d4fa1a1SMauro Carvalho Chehab } copy;
5349d4fa1a1SMauro Carvalho Chehab };
5359d4fa1a1SMauro Carvalho Chehab
5369d4fa1a1SMauro Carvalho Chehab /*
5379d4fa1a1SMauro Carvalho Chehab * The first frames (with comment Dynamic) can be dynamic or static
5389d4fa1a1SMauro Carvalho Chehab * The other frames (ref_in and below) can only be static
5399d4fa1a1SMauro Carvalho Chehab * Static means that the data address will not change during the life time
5409d4fa1a1SMauro Carvalho Chehab * of the associated pipe. Dynamic means that the data address can
5419d4fa1a1SMauro Carvalho Chehab * change with every (frame) iteration of the associated pipe
5429d4fa1a1SMauro Carvalho Chehab *
5439d4fa1a1SMauro Carvalho Chehab * s3a and dis are now also dynamic but (stil) handled separately
5449d4fa1a1SMauro Carvalho Chehab */
5459d4fa1a1SMauro Carvalho Chehab #define SH_CSS_NUM_DYNAMIC_FRAME_IDS (3)
5469d4fa1a1SMauro Carvalho Chehab
5479d4fa1a1SMauro Carvalho Chehab struct ia_css_frames_sp {
5489d4fa1a1SMauro Carvalho Chehab struct ia_css_frame_sp in;
5499d4fa1a1SMauro Carvalho Chehab struct ia_css_frame_sp out[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
5509d4fa1a1SMauro Carvalho Chehab struct ia_css_resolution effective_in_res;
5519d4fa1a1SMauro Carvalho Chehab struct ia_css_frame_sp out_vf;
5529d4fa1a1SMauro Carvalho Chehab struct ia_css_frame_sp_info internal_frame_info;
5539d4fa1a1SMauro Carvalho Chehab struct ia_css_buffer_sp s3a_buf;
5549d4fa1a1SMauro Carvalho Chehab struct ia_css_buffer_sp dvs_buf;
5559d4fa1a1SMauro Carvalho Chehab struct ia_css_buffer_sp metadata_buf;
5569d4fa1a1SMauro Carvalho Chehab };
5579d4fa1a1SMauro Carvalho Chehab
5589d4fa1a1SMauro Carvalho Chehab /* Information for a single pipeline stage for an ISP */
5599d4fa1a1SMauro Carvalho Chehab struct sh_css_isp_stage {
5609d4fa1a1SMauro Carvalho Chehab /*
5619d4fa1a1SMauro Carvalho Chehab * For compatibility and portabilty, only types
5629d4fa1a1SMauro Carvalho Chehab * from "stdint.h" are allowed
5639d4fa1a1SMauro Carvalho Chehab *
5649d4fa1a1SMauro Carvalho Chehab * Use of "enum" and "bool" is prohibited
5659d4fa1a1SMauro Carvalho Chehab * Multiple boolean flags can be stored in an
5669d4fa1a1SMauro Carvalho Chehab * integer
5679d4fa1a1SMauro Carvalho Chehab */
5689d4fa1a1SMauro Carvalho Chehab struct ia_css_blob_info blob_info;
5699d4fa1a1SMauro Carvalho Chehab struct ia_css_binary_info binary_info;
5709d4fa1a1SMauro Carvalho Chehab char binary_name[SH_CSS_MAX_BINARY_NAME];
5719d4fa1a1SMauro Carvalho Chehab struct ia_css_isp_param_css_segments mem_initializers;
5729d4fa1a1SMauro Carvalho Chehab };
5739d4fa1a1SMauro Carvalho Chehab
5749d4fa1a1SMauro Carvalho Chehab /* Information for a single pipeline stage */
5759d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_stage {
5769d4fa1a1SMauro Carvalho Chehab /*
5779d4fa1a1SMauro Carvalho Chehab * For compatibility and portabilty, only types
5789d4fa1a1SMauro Carvalho Chehab * from "stdint.h" are allowed
5799d4fa1a1SMauro Carvalho Chehab *
5809d4fa1a1SMauro Carvalho Chehab * Use of "enum" and "bool" is prohibited
5819d4fa1a1SMauro Carvalho Chehab * Multiple boolean flags can be stored in an
5829d4fa1a1SMauro Carvalho Chehab * integer
5839d4fa1a1SMauro Carvalho Chehab */
5849d4fa1a1SMauro Carvalho Chehab u8 num; /* Stage number */
5859d4fa1a1SMauro Carvalho Chehab u8 isp_online;
5869d4fa1a1SMauro Carvalho Chehab u8 isp_copy_vf;
5879d4fa1a1SMauro Carvalho Chehab u8 isp_copy_output;
5889d4fa1a1SMauro Carvalho Chehab u8 sp_enable_xnr;
5899d4fa1a1SMauro Carvalho Chehab u8 isp_deci_log_factor;
5909d4fa1a1SMauro Carvalho Chehab u8 isp_vf_downscale_bits;
5919d4fa1a1SMauro Carvalho Chehab u8 deinterleaved;
5929d4fa1a1SMauro Carvalho Chehab /*
5939d4fa1a1SMauro Carvalho Chehab * NOTE: Programming the input circuit can only be done at the
5949d4fa1a1SMauro Carvalho Chehab * start of a session. It is illegal to program it during execution
5959d4fa1a1SMauro Carvalho Chehab * The input circuit defines the connectivity
5969d4fa1a1SMauro Carvalho Chehab */
5979d4fa1a1SMauro Carvalho Chehab u8 program_input_circuit;
5989d4fa1a1SMauro Carvalho Chehab /* enum ia_css_pipeline_stage_sp_func func; */
5999d4fa1a1SMauro Carvalho Chehab u8 func;
6009d4fa1a1SMauro Carvalho Chehab /* The type of the pipe-stage */
6019d4fa1a1SMauro Carvalho Chehab /* enum sh_css_stage_type stage_type; */
6029d4fa1a1SMauro Carvalho Chehab u8 stage_type;
6039d4fa1a1SMauro Carvalho Chehab u8 num_stripes;
6049d4fa1a1SMauro Carvalho Chehab u8 isp_pipe_version;
6059d4fa1a1SMauro Carvalho Chehab struct {
6069d4fa1a1SMauro Carvalho Chehab u8 vf_output;
6079d4fa1a1SMauro Carvalho Chehab u8 s3a;
6089d4fa1a1SMauro Carvalho Chehab u8 sdis;
6099d4fa1a1SMauro Carvalho Chehab u8 dvs_stats;
6109d4fa1a1SMauro Carvalho Chehab u8 lace_stats;
6119d4fa1a1SMauro Carvalho Chehab } enable;
6129d4fa1a1SMauro Carvalho Chehab /* Add padding to come to a word boundary */
6139d4fa1a1SMauro Carvalho Chehab /* unsigned char padding[0]; */
6149d4fa1a1SMauro Carvalho Chehab
6159d4fa1a1SMauro Carvalho Chehab struct sh_css_crop_pos sp_out_crop_pos;
6169d4fa1a1SMauro Carvalho Chehab struct ia_css_frames_sp frames;
6179d4fa1a1SMauro Carvalho Chehab struct ia_css_resolution dvs_envelope;
6189d4fa1a1SMauro Carvalho Chehab struct sh_css_uds_info uds;
619100e8989SMauro Carvalho Chehab ia_css_ptr isp_stage_addr;
620100e8989SMauro Carvalho Chehab ia_css_ptr xmem_bin_addr;
621100e8989SMauro Carvalho Chehab ia_css_ptr xmem_map_addr;
6229d4fa1a1SMauro Carvalho Chehab
6239d4fa1a1SMauro Carvalho Chehab u16 top_cropping;
6249d4fa1a1SMauro Carvalho Chehab u16 row_stripes_height;
6259d4fa1a1SMauro Carvalho Chehab u16 row_stripes_overlap_lines;
6269d4fa1a1SMauro Carvalho Chehab u8 if_config_index; /* Which should be applied by this stage. */
6279d4fa1a1SMauro Carvalho Chehab };
6289d4fa1a1SMauro Carvalho Chehab
6299d4fa1a1SMauro Carvalho Chehab /*
6309d4fa1a1SMauro Carvalho Chehab * Time: 2012-07-19, 17:40.
6319d4fa1a1SMauro Carvalho Chehab * Note: Add a new data memeber "debug" in "sh_css_sp_group". This
6329d4fa1a1SMauro Carvalho Chehab * data member is used to pass the debugging command from the
6339d4fa1a1SMauro Carvalho Chehab * Host to the SP.
6349d4fa1a1SMauro Carvalho Chehab *
6359d4fa1a1SMauro Carvalho Chehab * Time: Before 2012-07-19.
6369d4fa1a1SMauro Carvalho Chehab * Note:
6379d4fa1a1SMauro Carvalho Chehab * Group all host initialized SP variables into this struct.
6389d4fa1a1SMauro Carvalho Chehab * This is initialized every stage through dma.
6399d4fa1a1SMauro Carvalho Chehab * The stage part itself is transferred through sh_css_sp_stage.
6409d4fa1a1SMauro Carvalho Chehab */
6419d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_group {
6429d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_config config;
6439d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_pipeline pipe[SH_CSS_MAX_SP_THREADS];
644641c2292SMauro Carvalho Chehab #if defined(ISP2401)
6459d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_pipeline_io pipe_io[SH_CSS_MAX_SP_THREADS];
6469d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_pipeline_io_status pipe_io_status;
6479d4fa1a1SMauro Carvalho Chehab #endif
6489d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_debug_command debug;
6499d4fa1a1SMauro Carvalho Chehab };
6509d4fa1a1SMauro Carvalho Chehab
6519d4fa1a1SMauro Carvalho Chehab /* Data in SP dmem that is set from the host every stage. */
6529d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_per_frame_data {
6539d4fa1a1SMauro Carvalho Chehab /* ddr address of sp_group and sp_stage */
654100e8989SMauro Carvalho Chehab ia_css_ptr sp_group_addr;
6559d4fa1a1SMauro Carvalho Chehab };
6569d4fa1a1SMauro Carvalho Chehab
6579d4fa1a1SMauro Carvalho Chehab #define SH_CSS_NUM_SDW_IRQS 3
6589d4fa1a1SMauro Carvalho Chehab
6599d4fa1a1SMauro Carvalho Chehab /* Output data from SP to css */
6609d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_output {
6619d4fa1a1SMauro Carvalho Chehab unsigned int bin_copy_bytes_copied;
6629d4fa1a1SMauro Carvalho Chehab #if SP_DEBUG != SP_DEBUG_NONE
6639d4fa1a1SMauro Carvalho Chehab struct sh_css_sp_debug_state debug;
6649d4fa1a1SMauro Carvalho Chehab #endif
6659d4fa1a1SMauro Carvalho Chehab unsigned int sw_interrupt_value[SH_CSS_NUM_SDW_IRQS];
6669d4fa1a1SMauro Carvalho Chehab };
6679d4fa1a1SMauro Carvalho Chehab
6689d4fa1a1SMauro Carvalho Chehab /**
6699d4fa1a1SMauro Carvalho Chehab * @brief Data structure for the circular buffer.
6709d4fa1a1SMauro Carvalho Chehab * The circular buffer is empty if "start == end". The
6719d4fa1a1SMauro Carvalho Chehab * circular buffer is full if "(end + 1) % size == start".
6729d4fa1a1SMauro Carvalho Chehab */
6739d4fa1a1SMauro Carvalho Chehab /* Variable Sized Buffer Queue Elements */
6749d4fa1a1SMauro Carvalho Chehab
6759d4fa1a1SMauro Carvalho Chehab #define IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE 6
6769d4fa1a1SMauro Carvalho Chehab #define IA_CSS_NUM_ELEMS_HOST2SP_PARAM_QUEUE 3
6779d4fa1a1SMauro Carvalho Chehab #define IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE 6
6789d4fa1a1SMauro Carvalho Chehab
6799d4fa1a1SMauro Carvalho Chehab /* sp-to-host queue is expected to be emptied in ISR since
6809d4fa1a1SMauro Carvalho Chehab * it is used instead of HW interrupts (due to HW design issue).
6819d4fa1a1SMauro Carvalho Chehab * We need one queue element per CSI port. */
6829d4fa1a1SMauro Carvalho Chehab #define IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS)
6839d4fa1a1SMauro Carvalho Chehab /* The host-to-sp queue needs to allow for some delay
6849d4fa1a1SMauro Carvalho Chehab * in the emptying of this queue in the SP since there is no
6859d4fa1a1SMauro Carvalho Chehab * separate SP thread for this. */
6869d4fa1a1SMauro Carvalho Chehab #define IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS)
6879d4fa1a1SMauro Carvalho Chehab
6889d4fa1a1SMauro Carvalho Chehab #define IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE 13
6899d4fa1a1SMauro Carvalho Chehab #define IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE 19
6909d4fa1a1SMauro Carvalho Chehab #define IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE 26 /* holds events for all type of buffers, hence deeper */
6919d4fa1a1SMauro Carvalho Chehab
6929d4fa1a1SMauro Carvalho Chehab struct sh_css_hmm_buffer {
6939d4fa1a1SMauro Carvalho Chehab union {
6949d4fa1a1SMauro Carvalho Chehab struct ia_css_isp_3a_statistics s3a;
6959d4fa1a1SMauro Carvalho Chehab struct ia_css_isp_dvs_statistics dis;
696100e8989SMauro Carvalho Chehab ia_css_ptr skc_dvs_statistics;
697100e8989SMauro Carvalho Chehab ia_css_ptr lace_stat;
6989d4fa1a1SMauro Carvalho Chehab struct ia_css_metadata metadata;
6999d4fa1a1SMauro Carvalho Chehab struct frame_data_wrapper {
700100e8989SMauro Carvalho Chehab ia_css_ptr frame_data;
7019d4fa1a1SMauro Carvalho Chehab u32 flashed;
7029d4fa1a1SMauro Carvalho Chehab u32 exp_id;
7039d4fa1a1SMauro Carvalho Chehab u32 isp_parameters_id; /** Unique ID to track which config was
7049d4fa1a1SMauro Carvalho Chehab actually applied to a particular frame */
7059d4fa1a1SMauro Carvalho Chehab } frame;
706100e8989SMauro Carvalho Chehab ia_css_ptr ddr_ptrs;
7079d4fa1a1SMauro Carvalho Chehab } payload;
7089d4fa1a1SMauro Carvalho Chehab /*
7099d4fa1a1SMauro Carvalho Chehab * kernel_ptr is present for host administration purposes only.
7109d4fa1a1SMauro Carvalho Chehab * type is uint64_t in order to be 64-bit host compatible.
7119d4fa1a1SMauro Carvalho Chehab * uint64_t does not exist on SP/ISP.
7129d4fa1a1SMauro Carvalho Chehab * Size of the struct is checked by sp.hive.c.
7139d4fa1a1SMauro Carvalho Chehab */
7149d4fa1a1SMauro Carvalho Chehab CSS_ALIGN(u64 cookie_ptr, 8); /* TODO: check if this alignment is needed */
7159d4fa1a1SMauro Carvalho Chehab u64 kernel_ptr;
7169d4fa1a1SMauro Carvalho Chehab struct ia_css_time_meas timing_data;
7179d4fa1a1SMauro Carvalho Chehab clock_value_t isys_eof_clock_tick;
7189d4fa1a1SMauro Carvalho Chehab };
7199d4fa1a1SMauro Carvalho Chehab
7209d4fa1a1SMauro Carvalho Chehab #define SIZE_OF_FRAME_STRUCT \
7219d4fa1a1SMauro Carvalho Chehab (SIZE_OF_HRT_VADDRESS + \
7229d4fa1a1SMauro Carvalho Chehab (3 * sizeof(uint32_t)))
7239d4fa1a1SMauro Carvalho Chehab
7249d4fa1a1SMauro Carvalho Chehab #define SIZE_OF_PAYLOAD_UNION \
7259d4fa1a1SMauro Carvalho Chehab (MAX(MAX(MAX(MAX( \
7269d4fa1a1SMauro Carvalho Chehab SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT, \
7279d4fa1a1SMauro Carvalho Chehab SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT), \
7289d4fa1a1SMauro Carvalho Chehab SIZE_OF_IA_CSS_METADATA_STRUCT), \
7299d4fa1a1SMauro Carvalho Chehab SIZE_OF_FRAME_STRUCT), \
7309d4fa1a1SMauro Carvalho Chehab SIZE_OF_HRT_VADDRESS))
7319d4fa1a1SMauro Carvalho Chehab
7329d4fa1a1SMauro Carvalho Chehab /* Do not use sizeof(uint64_t) since that does not exist of SP */
7339d4fa1a1SMauro Carvalho Chehab #define SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT \
7349d4fa1a1SMauro Carvalho Chehab (SIZE_OF_PAYLOAD_UNION + \
7359d4fa1a1SMauro Carvalho Chehab CALC_ALIGNMENT_MEMBER(SIZE_OF_PAYLOAD_UNION, 8) + \
7369d4fa1a1SMauro Carvalho Chehab 8 + \
7379d4fa1a1SMauro Carvalho Chehab 8 + \
7389d4fa1a1SMauro Carvalho Chehab SIZE_OF_IA_CSS_TIME_MEAS_STRUCT + \
7399d4fa1a1SMauro Carvalho Chehab SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT + \
7409d4fa1a1SMauro Carvalho Chehab CALC_ALIGNMENT_MEMBER(SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT, 8))
7419d4fa1a1SMauro Carvalho Chehab
7429d4fa1a1SMauro Carvalho Chehab enum sh_css_queue_type {
7439d4fa1a1SMauro Carvalho Chehab sh_css_invalid_queue_type = -1,
7449d4fa1a1SMauro Carvalho Chehab sh_css_host2sp_buffer_queue,
7459d4fa1a1SMauro Carvalho Chehab sh_css_sp2host_buffer_queue,
7469d4fa1a1SMauro Carvalho Chehab sh_css_host2sp_psys_event_queue,
7479d4fa1a1SMauro Carvalho Chehab sh_css_sp2host_psys_event_queue,
7489d4fa1a1SMauro Carvalho Chehab sh_css_sp2host_isys_event_queue,
7499d4fa1a1SMauro Carvalho Chehab sh_css_host2sp_isys_event_queue,
7509d4fa1a1SMauro Carvalho Chehab sh_css_host2sp_tag_cmd_queue,
7519d4fa1a1SMauro Carvalho Chehab };
7529d4fa1a1SMauro Carvalho Chehab
7539d4fa1a1SMauro Carvalho Chehab struct sh_css_event_irq_mask {
7549d4fa1a1SMauro Carvalho Chehab u16 or_mask;
7559d4fa1a1SMauro Carvalho Chehab u16 and_mask;
7569d4fa1a1SMauro Carvalho Chehab };
7579d4fa1a1SMauro Carvalho Chehab
7589d4fa1a1SMauro Carvalho Chehab #define SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT \
7599d4fa1a1SMauro Carvalho Chehab (2 * sizeof(uint16_t))
7609d4fa1a1SMauro Carvalho Chehab
7619d4fa1a1SMauro Carvalho Chehab struct host_sp_communication {
7629d4fa1a1SMauro Carvalho Chehab /*
7639d4fa1a1SMauro Carvalho Chehab * Don't use enum host2sp_commands, because the sizeof an enum is
7649d4fa1a1SMauro Carvalho Chehab * compiler dependent and thus non-portable
7659d4fa1a1SMauro Carvalho Chehab */
7669d4fa1a1SMauro Carvalho Chehab u32 host2sp_command;
7679d4fa1a1SMauro Carvalho Chehab
7689d4fa1a1SMauro Carvalho Chehab /*
7699d4fa1a1SMauro Carvalho Chehab * The frame buffers that are reused by the
7709d4fa1a1SMauro Carvalho Chehab * copy pipe in the offline preview mode.
7719d4fa1a1SMauro Carvalho Chehab *
7729d4fa1a1SMauro Carvalho Chehab * host2sp_offline_frames[0]: the input frame of the preview pipe.
7739d4fa1a1SMauro Carvalho Chehab * host2sp_offline_frames[1]: the output frame of the copy pipe.
7749d4fa1a1SMauro Carvalho Chehab *
7759d4fa1a1SMauro Carvalho Chehab * TODO:
7769d4fa1a1SMauro Carvalho Chehab * Remove it when the Host and the SP is decoupled.
7779d4fa1a1SMauro Carvalho Chehab */
778100e8989SMauro Carvalho Chehab ia_css_ptr host2sp_offline_frames[NUM_CONTINUOUS_FRAMES];
779100e8989SMauro Carvalho Chehab ia_css_ptr host2sp_offline_metadata[NUM_CONTINUOUS_FRAMES];
7809d4fa1a1SMauro Carvalho Chehab
781100e8989SMauro Carvalho Chehab ia_css_ptr host2sp_mipi_frames[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM];
782100e8989SMauro Carvalho Chehab ia_css_ptr host2sp_mipi_metadata[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM];
7839d4fa1a1SMauro Carvalho Chehab u32 host2sp_num_mipi_frames[N_CSI_PORTS];
7849d4fa1a1SMauro Carvalho Chehab u32 host2sp_cont_avail_num_raw_frames;
7859d4fa1a1SMauro Carvalho Chehab u32 host2sp_cont_extra_num_raw_frames;
7869d4fa1a1SMauro Carvalho Chehab u32 host2sp_cont_target_num_raw_frames;
7879d4fa1a1SMauro Carvalho Chehab struct sh_css_event_irq_mask host2sp_event_irq_mask[NR_OF_PIPELINES];
7889d4fa1a1SMauro Carvalho Chehab
7899d4fa1a1SMauro Carvalho Chehab };
7909d4fa1a1SMauro Carvalho Chehab
7919d4fa1a1SMauro Carvalho Chehab #define SIZE_OF_HOST_SP_COMMUNICATION_STRUCT \
7929d4fa1a1SMauro Carvalho Chehab (sizeof(uint32_t) + \
7939d4fa1a1SMauro Carvalho Chehab (NUM_CONTINUOUS_FRAMES * SIZE_OF_HRT_VADDRESS * 2) + \
7949d4fa1a1SMauro Carvalho Chehab (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM * SIZE_OF_HRT_VADDRESS * 2) + \
7959d4fa1a1SMauro Carvalho Chehab ((3 + N_CSI_PORTS) * sizeof(uint32_t)) + \
7969d4fa1a1SMauro Carvalho Chehab (NR_OF_PIPELINES * SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT))
7979d4fa1a1SMauro Carvalho Chehab
7989d4fa1a1SMauro Carvalho Chehab struct host_sp_queues {
7999d4fa1a1SMauro Carvalho Chehab /*
8009d4fa1a1SMauro Carvalho Chehab * Queues for the dynamic frame information,
8019d4fa1a1SMauro Carvalho Chehab * i.e. the "in_frame" buffer, the "out_frame"
8029d4fa1a1SMauro Carvalho Chehab * buffer and the "vf_out_frame" buffer.
8039d4fa1a1SMauro Carvalho Chehab */
8049d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_desc_t host2sp_buffer_queues_desc
8059d4fa1a1SMauro Carvalho Chehab [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES];
8069d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_elem_t host2sp_buffer_queues_elems
8079d4fa1a1SMauro Carvalho Chehab [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]
8089d4fa1a1SMauro Carvalho Chehab [IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE];
8099d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_desc_t sp2host_buffer_queues_desc
8109d4fa1a1SMauro Carvalho Chehab [SH_CSS_MAX_NUM_QUEUES];
8119d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_elem_t sp2host_buffer_queues_elems
8129d4fa1a1SMauro Carvalho Chehab [SH_CSS_MAX_NUM_QUEUES][IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE];
8139d4fa1a1SMauro Carvalho Chehab
8149d4fa1a1SMauro Carvalho Chehab /*
8159d4fa1a1SMauro Carvalho Chehab * The queues for the events.
8169d4fa1a1SMauro Carvalho Chehab */
8179d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_desc_t host2sp_psys_event_queue_desc;
8189d4fa1a1SMauro Carvalho Chehab
8199d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_elem_t host2sp_psys_event_queue_elems
8209d4fa1a1SMauro Carvalho Chehab [IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE];
8219d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_desc_t sp2host_psys_event_queue_desc;
8229d4fa1a1SMauro Carvalho Chehab
8239d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_elem_t sp2host_psys_event_queue_elems
8249d4fa1a1SMauro Carvalho Chehab [IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE];
8259d4fa1a1SMauro Carvalho Chehab
8269d4fa1a1SMauro Carvalho Chehab /*
8279d4fa1a1SMauro Carvalho Chehab * The queues for the ISYS events.
8289d4fa1a1SMauro Carvalho Chehab */
8299d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_desc_t host2sp_isys_event_queue_desc;
8309d4fa1a1SMauro Carvalho Chehab
8319d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_elem_t host2sp_isys_event_queue_elems
8329d4fa1a1SMauro Carvalho Chehab [IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE];
8339d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_desc_t sp2host_isys_event_queue_desc;
8349d4fa1a1SMauro Carvalho Chehab
8359d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_elem_t sp2host_isys_event_queue_elems
8369d4fa1a1SMauro Carvalho Chehab [IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE];
8379d4fa1a1SMauro Carvalho Chehab /*
8389d4fa1a1SMauro Carvalho Chehab * The queue for the tagger commands.
8399d4fa1a1SMauro Carvalho Chehab * CHECK: are these last two present on the 2401 ?
8409d4fa1a1SMauro Carvalho Chehab */
8419d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_desc_t host2sp_tag_cmd_queue_desc;
8429d4fa1a1SMauro Carvalho Chehab
8439d4fa1a1SMauro Carvalho Chehab ia_css_circbuf_elem_t host2sp_tag_cmd_queue_elems
8449d4fa1a1SMauro Carvalho Chehab [IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE];
8459d4fa1a1SMauro Carvalho Chehab };
8469d4fa1a1SMauro Carvalho Chehab
8479d4fa1a1SMauro Carvalho Chehab #define SIZE_OF_QUEUES_ELEMS \
8489d4fa1a1SMauro Carvalho Chehab (SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT * \
8499d4fa1a1SMauro Carvalho Chehab ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE) + \
8509d4fa1a1SMauro Carvalho Chehab (SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE) + \
8519d4fa1a1SMauro Carvalho Chehab (IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE) + \
8529d4fa1a1SMauro Carvalho Chehab (IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE) + \
8539d4fa1a1SMauro Carvalho Chehab (IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE) + \
8549d4fa1a1SMauro Carvalho Chehab (IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE) + \
8559d4fa1a1SMauro Carvalho Chehab (IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE)))
8569d4fa1a1SMauro Carvalho Chehab
8579d4fa1a1SMauro Carvalho Chehab #define IA_CSS_NUM_CIRCBUF_DESCS 5
8589d4fa1a1SMauro Carvalho Chehab
8599d4fa1a1SMauro Carvalho Chehab #define SIZE_OF_QUEUES_DESC \
8609d4fa1a1SMauro Carvalho Chehab ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * \
8619d4fa1a1SMauro Carvalho Chehab SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \
8629d4fa1a1SMauro Carvalho Chehab (SH_CSS_MAX_NUM_QUEUES * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \
8639d4fa1a1SMauro Carvalho Chehab (IA_CSS_NUM_CIRCBUF_DESCS * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT))
8649d4fa1a1SMauro Carvalho Chehab
8659d4fa1a1SMauro Carvalho Chehab #define SIZE_OF_HOST_SP_QUEUES_STRUCT \
8669d4fa1a1SMauro Carvalho Chehab (SIZE_OF_QUEUES_ELEMS + SIZE_OF_QUEUES_DESC)
8679d4fa1a1SMauro Carvalho Chehab
86801cc2ec6SMauro Carvalho Chehab extern int __printf(1, 0) (*sh_css_printf)(const char *fmt, va_list args);
8699d4fa1a1SMauro Carvalho Chehab
sh_css_print(const char * fmt,...)87001cc2ec6SMauro Carvalho Chehab static inline void __printf(1, 2) sh_css_print(const char *fmt, ...)
8719d4fa1a1SMauro Carvalho Chehab {
8729d4fa1a1SMauro Carvalho Chehab va_list ap;
8739d4fa1a1SMauro Carvalho Chehab
8749d4fa1a1SMauro Carvalho Chehab if (sh_css_printf) {
8759d4fa1a1SMauro Carvalho Chehab va_start(ap, fmt);
8769d4fa1a1SMauro Carvalho Chehab sh_css_printf(fmt, ap);
8779d4fa1a1SMauro Carvalho Chehab va_end(ap);
8789d4fa1a1SMauro Carvalho Chehab }
8799d4fa1a1SMauro Carvalho Chehab }
8809d4fa1a1SMauro Carvalho Chehab
sh_css_vprint(const char * fmt,va_list args)88101cc2ec6SMauro Carvalho Chehab static inline void __printf(1, 0) sh_css_vprint(const char *fmt, va_list args)
8829d4fa1a1SMauro Carvalho Chehab {
8839d4fa1a1SMauro Carvalho Chehab if (sh_css_printf)
8849d4fa1a1SMauro Carvalho Chehab sh_css_printf(fmt, args);
8859d4fa1a1SMauro Carvalho Chehab }
8869d4fa1a1SMauro Carvalho Chehab
8879d4fa1a1SMauro Carvalho Chehab /* The following #if is there because this header file is also included
8889d4fa1a1SMauro Carvalho Chehab by SP and ISP code but they do not need this data and HIVECC has alignment
8899d4fa1a1SMauro Carvalho Chehab issue with the firmware struct/union's.
8909d4fa1a1SMauro Carvalho Chehab More permanent solution will be to refactor this include.
8919d4fa1a1SMauro Carvalho Chehab */
892100e8989SMauro Carvalho Chehab ia_css_ptr sh_css_params_ddr_address_map(void);
8939d4fa1a1SMauro Carvalho Chehab
89441022d35SMauro Carvalho Chehab int
8959d4fa1a1SMauro Carvalho Chehab sh_css_params_init(void);
8969d4fa1a1SMauro Carvalho Chehab
8979d4fa1a1SMauro Carvalho Chehab void
8989d4fa1a1SMauro Carvalho Chehab sh_css_params_uninit(void);
8999d4fa1a1SMauro Carvalho Chehab
9009d4fa1a1SMauro Carvalho Chehab void
9019d4fa1a1SMauro Carvalho Chehab sh_css_binary_args_reset(struct sh_css_binary_args *args);
9029d4fa1a1SMauro Carvalho Chehab
9039d4fa1a1SMauro Carvalho Chehab /* Check two frames for equality (format, resolution, bits per element) */
9049d4fa1a1SMauro Carvalho Chehab bool
9059d4fa1a1SMauro Carvalho Chehab sh_css_frame_equal_types(const struct ia_css_frame *frame_a,
9069d4fa1a1SMauro Carvalho Chehab const struct ia_css_frame *frame_b);
9079d4fa1a1SMauro Carvalho Chehab
9089d4fa1a1SMauro Carvalho Chehab bool
9099d4fa1a1SMauro Carvalho Chehab sh_css_frame_info_equal_resolution(const struct ia_css_frame_info *info_a,
9109d4fa1a1SMauro Carvalho Chehab const struct ia_css_frame_info *info_b);
9119d4fa1a1SMauro Carvalho Chehab
9129d4fa1a1SMauro Carvalho Chehab void
9139d4fa1a1SMauro Carvalho Chehab sh_css_capture_enable_bayer_downscaling(bool enable);
9149d4fa1a1SMauro Carvalho Chehab
9159d4fa1a1SMauro Carvalho Chehab void
9169d4fa1a1SMauro Carvalho Chehab sh_css_binary_print(const struct ia_css_binary *binary);
9179d4fa1a1SMauro Carvalho Chehab
9189d4fa1a1SMauro Carvalho Chehab /* aligned argument of sh_css_frame_info_set_width can be used for an extra alignment requirement.
9199d4fa1a1SMauro Carvalho Chehab When 0, no extra alignment is done. */
9209d4fa1a1SMauro Carvalho Chehab void
9219d4fa1a1SMauro Carvalho Chehab sh_css_frame_info_set_width(struct ia_css_frame_info *info,
9229d4fa1a1SMauro Carvalho Chehab unsigned int width,
9239d4fa1a1SMauro Carvalho Chehab unsigned int aligned);
9249d4fa1a1SMauro Carvalho Chehab
925641c2292SMauro Carvalho Chehab #if !defined(ISP2401)
9269d4fa1a1SMauro Carvalho Chehab
9279d4fa1a1SMauro Carvalho Chehab unsigned int
9289d4fa1a1SMauro Carvalho Chehab sh_css_get_mipi_sizes_for_check(const unsigned int port,
9299d4fa1a1SMauro Carvalho Chehab const unsigned int idx);
9309d4fa1a1SMauro Carvalho Chehab
9319d4fa1a1SMauro Carvalho Chehab #endif
9329d4fa1a1SMauro Carvalho Chehab
933100e8989SMauro Carvalho Chehab ia_css_ptr
9349d4fa1a1SMauro Carvalho Chehab sh_css_store_sp_group_to_ddr(void);
9359d4fa1a1SMauro Carvalho Chehab
936100e8989SMauro Carvalho Chehab ia_css_ptr
9379d4fa1a1SMauro Carvalho Chehab sh_css_store_sp_stage_to_ddr(unsigned int pipe, unsigned int stage);
9389d4fa1a1SMauro Carvalho Chehab
939100e8989SMauro Carvalho Chehab ia_css_ptr
9409d4fa1a1SMauro Carvalho Chehab sh_css_store_isp_stage_to_ddr(unsigned int pipe, unsigned int stage);
9419d4fa1a1SMauro Carvalho Chehab
9429d4fa1a1SMauro Carvalho Chehab void
9439d4fa1a1SMauro Carvalho Chehab sh_css_update_uds_and_crop_info(
9449d4fa1a1SMauro Carvalho Chehab const struct ia_css_binary_info *info,
9459d4fa1a1SMauro Carvalho Chehab const struct ia_css_frame_info *in_frame_info,
9469d4fa1a1SMauro Carvalho Chehab const struct ia_css_frame_info *out_frame_info,
9479d4fa1a1SMauro Carvalho Chehab const struct ia_css_resolution *dvs_env,
9489d4fa1a1SMauro Carvalho Chehab const struct ia_css_dz_config *zoom,
9499d4fa1a1SMauro Carvalho Chehab const struct ia_css_vector *motion_vector,
9509d4fa1a1SMauro Carvalho Chehab struct sh_css_uds_info *uds, /* out */
9519d4fa1a1SMauro Carvalho Chehab struct sh_css_crop_pos *sp_out_crop_pos, /* out */
9529d4fa1a1SMauro Carvalho Chehab
9539d4fa1a1SMauro Carvalho Chehab bool enable_zoom
9549d4fa1a1SMauro Carvalho Chehab );
9559d4fa1a1SMauro Carvalho Chehab
9569d4fa1a1SMauro Carvalho Chehab void
9579d4fa1a1SMauro Carvalho Chehab sh_css_invalidate_shading_tables(struct ia_css_stream *stream);
9589d4fa1a1SMauro Carvalho Chehab
9599d4fa1a1SMauro Carvalho Chehab struct ia_css_pipeline *
9609d4fa1a1SMauro Carvalho Chehab ia_css_pipe_get_pipeline(const struct ia_css_pipe *pipe);
9619d4fa1a1SMauro Carvalho Chehab
9629d4fa1a1SMauro Carvalho Chehab unsigned int
9639d4fa1a1SMauro Carvalho Chehab ia_css_pipe_get_pipe_num(const struct ia_css_pipe *pipe);
9649d4fa1a1SMauro Carvalho Chehab
9659d4fa1a1SMauro Carvalho Chehab unsigned int
9669d4fa1a1SMauro Carvalho Chehab ia_css_pipe_get_isp_pipe_version(const struct ia_css_pipe *pipe);
9679d4fa1a1SMauro Carvalho Chehab
9689d4fa1a1SMauro Carvalho Chehab bool
9699d4fa1a1SMauro Carvalho Chehab sh_css_continuous_is_enabled(uint8_t pipe_num);
9709d4fa1a1SMauro Carvalho Chehab
9719d4fa1a1SMauro Carvalho Chehab struct ia_css_pipe *
9729d4fa1a1SMauro Carvalho Chehab find_pipe_by_num(uint32_t pipe_num);
9739d4fa1a1SMauro Carvalho Chehab
974641c2292SMauro Carvalho Chehab #ifdef ISP2401
9759d4fa1a1SMauro Carvalho Chehab void
9769d4fa1a1SMauro Carvalho Chehab ia_css_get_crop_offsets(
9779d4fa1a1SMauro Carvalho Chehab struct ia_css_pipe *pipe,
9789d4fa1a1SMauro Carvalho Chehab struct ia_css_frame_info *in_frame);
9799d4fa1a1SMauro Carvalho Chehab #endif
9809d4fa1a1SMauro Carvalho Chehab
9819d4fa1a1SMauro Carvalho Chehab #endif /* _SH_CSS_INTERNAL_H_ */
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