Home
last modified time | relevance | path

Searched refs:opc (Results 1 – 25 of 52) sorted by relevance

123

/openbmc/qemu/include/hw/xtensa/
H A Dxtensa-isa.h378 xtensa_insnbuf slotbuf, xtensa_opcode opc);
383 const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc);
403 int xtensa_opcode_is_branch(xtensa_isa isa, xtensa_opcode opc);
405 int xtensa_opcode_is_jump(xtensa_isa isa, xtensa_opcode opc);
407 int xtensa_opcode_is_loop(xtensa_isa isa, xtensa_opcode opc);
409 int xtensa_opcode_is_call(xtensa_isa isa, xtensa_opcode opc);
418 int xtensa_opcode_num_operands(xtensa_isa isa, xtensa_opcode opc);
420 int xtensa_opcode_num_stateOperands(xtensa_isa isa, xtensa_opcode opc);
422 int xtensa_opcode_num_interfaceOperands(xtensa_isa isa, xtensa_opcode opc);
438 int xtensa_opcode_num_funcUnit_uses(xtensa_isa isa, xtensa_opcode opc);
[all …]
/openbmc/qemu/target/xtensa/
H A Dxtensa-isa.c662 xtensa_opcode opc; in xtensa_opcode_decode() local
669 opc = (intisa->slots[slot_id].opcode_decode_fn) (slotbuf); in xtensa_opcode_decode()
670 if (opc != XTENSA_UNDEFINED) { in xtensa_opcode_decode()
671 return opc; in xtensa_opcode_decode()
681 xtensa_insnbuf slotbuf, xtensa_opcode opc) in xtensa_opcode_encode() argument
689 CHECK_OPCODE(intisa, opc, -1); in xtensa_opcode_encode()
692 encode_fn = intisa->opcodes[opc].encode_fns[slot_id]; in xtensa_opcode_encode()
697 intisa->opcodes[opc].name, slot, intisa->formats[fmt].name); in xtensa_opcode_encode()
705 const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc) in xtensa_opcode_name() argument
709 CHECK_OPCODE(intisa, opc, NULL); in xtensa_opcode_name()
[all …]
/openbmc/qemu/disas/
H A Dxtensa.c81 xtensa_opcode opc; in print_insn_xtensa() local
88 opc = xtensa_opcode_decode(isa, fmt, slot, slotbuf); in print_insn_xtensa()
89 if (opc == XTENSA_UNDEFINED) { in print_insn_xtensa()
93 opnds = xtensa_opcode_num_operands(isa, opc); in print_insn_xtensa()
95 info->fprintf_func(info->stream, "%s", xtensa_opcode_name(isa, opc)); in print_insn_xtensa()
98 if (xtensa_operand_is_visible(isa, opc, opnd)) { in print_insn_xtensa()
103 xtensa_operand_get_field(isa, opc, opnd, fmt, slot, in print_insn_xtensa()
105 rc = xtensa_operand_decode(isa, opc, opnd, &v); in print_insn_xtensa()
108 } else if (xtensa_operand_is_register(isa, opc, opnd)) { in print_insn_xtensa()
109 xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd); in print_insn_xtensa()
[all …]
/openbmc/qemu/tcg/
H A Dtcg-op-vec.c69 TCGOpcode opc = *list; in tcg_can_emit_vecop_list() local
72 switch (opc) { in tcg_can_emit_vecop_list()
92 if (tcg_can_emit_vec_op(opc, type, vece)) { in tcg_can_emit_vecop_list()
101 switch (opc) { in tcg_can_emit_vecop_list()
144 void vec_gen_2(TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, TCGArg a) in vec_gen_2() argument
146 TCGOp *op = tcg_emit_op(opc, 2); in vec_gen_2()
153 void vec_gen_3(TCGOpcode opc, TCGType type, unsigned vece, in vec_gen_3() argument
156 TCGOp *op = tcg_emit_op(opc, 3); in vec_gen_3()
164 void vec_gen_4(TCGOpcode opc, TCGType type, unsigned vece, in vec_gen_4() argument
167 TCGOp *op = tcg_emit_op(opc, 4); in vec_gen_4()
[all …]
H A Doptimize.c346 TCGOpcode opc, unsigned narg) in opt_insert_after() argument
348 return tcg_op_insert_after(ctx->tcg, op, opc, ctx->type, narg); in opt_insert_after()
352 TCGOpcode opc, unsigned narg) in opt_insert_before() argument
354 return tcg_op_insert_before(ctx->tcg, op, opc, ctx->type, narg); in opt_insert_before()
388 op->opc = new_op; in tcg_opt_gen_mov()
984 const TCGOpDef *def = &tcg_op_defs[op->opc]; in finish_folding()
1011 t = do_constant_folding(op->opc, ctx->type, t, 0); in fold_const1()
1023 t1 = do_constant_folding(op->opc, ctx->type, t1, t2); in fold_const2()
1051 const TCGOpDef *def = &tcg_op_defs[op->opc]; in fold_masks_zosa_int()
1164 op->opc = not_op; in fold_to_not()
[all …]
H A Dtcg-op.c40 TCGOp * NI tcg_gen_op1(TCGOpcode opc, TCGType type, TCGArg a1) in tcg_gen_op1() argument
42 TCGOp *op = tcg_emit_op(opc, 1); in tcg_gen_op1()
48 TCGOp * NI tcg_gen_op2(TCGOpcode opc, TCGType type, TCGArg a1, TCGArg a2) in tcg_gen_op2() argument
50 TCGOp *op = tcg_emit_op(opc, 2); in tcg_gen_op2()
57 TCGOp * NI tcg_gen_op3(TCGOpcode opc, TCGType type, TCGArg a1, in tcg_gen_op3() argument
60 TCGOp *op = tcg_emit_op(opc, 3); in tcg_gen_op3()
68 TCGOp * NI tcg_gen_op4(TCGOpcode opc, TCGType type, TCGArg a1, TCGArg a2, in tcg_gen_op4() argument
71 TCGOp *op = tcg_emit_op(opc, 4); in tcg_gen_op4()
80 TCGOp * NI tcg_gen_op5(TCGOpcode opc, TCGType type, TCGArg a1, TCGArg a2, in tcg_gen_op5() argument
83 TCGOp *op = tcg_emit_op(opc, 5); in tcg_gen_op5()
[all …]
H A Dtcg.c149 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
169 static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, in tcg_out_vec_op() argument
239 static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc,
2616 static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs);
2945 c = op->opc; in tcg_dump_ops()
3511 TCGOpcode opc = op->opc; in opcode_args_ct() local
3514 const TCGOpDef *def = &tcg_op_defs[opc]; in opcode_args_ct()
3515 const TCGOutOp *outop = all_outop[opc]; in opcode_args_ct()
3528 con_set = tcg_target_op_def(opc, type, flags); in opcode_args_ct()
3556 switch (op->opc) { in tcg_op_remove()
[all …]
/openbmc/u-boot/drivers/mmc/
H A Dsh_mmcif.c337 u32 opc = cmd->cmdidx; in sh_mmcif_set_cmd() local
358 if (opc == MMC_CMD_SWITCH) in sh_mmcif_set_cmd()
380 if (opc == MMC_CMD_WRITE_SINGLE_BLOCK || in sh_mmcif_set_cmd()
381 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) in sh_mmcif_set_cmd()
384 if (opc == MMC_CMD_READ_MULTIPLE_BLOCK || in sh_mmcif_set_cmd()
385 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) { in sh_mmcif_set_cmd()
390 if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID || in sh_mmcif_set_cmd()
391 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID) in sh_mmcif_set_cmd()
394 if (opc == MMC_CMD_SEND_OP_COND) in sh_mmcif_set_cmd()
397 if (opc == MMC_CMD_ALL_SEND_CID || in sh_mmcif_set_cmd()
[all …]
H A Dsh_sdhi.c477 struct mmc_data *data, unsigned short opc) in sh_sdhi_set_cmd() argument
482 return opc | BIT(6); in sh_sdhi_set_cmd()
485 switch (opc) { in sh_sdhi_set_cmd()
487 return opc | (data ? 0x1c00 : 0x40); in sh_sdhi_set_cmd()
489 return opc | (data ? 0x1c00 : 0); in sh_sdhi_set_cmd()
491 return opc | 0x0700; in sh_sdhi_set_cmd()
495 return opc; in sh_sdhi_set_cmd()
500 struct mmc_data *data, unsigned short opc) in sh_sdhi_data_trans() argument
504 switch (opc) { in sh_sdhi_data_trans()
510 opc); in sh_sdhi_data_trans()
[all …]
/openbmc/openbmc/poky/meta/recipes-devtools/binutils/binutils/
H A D0007-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch13 opcodes/ppc-opc.c | 4 +---
16 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
18 --- a/opcodes/ppc-opc.c
19 +++ b/opcodes/ppc-opc.c
/openbmc/qemu/target/arm/tcg/
H A Dtranslate-a32.h107 TCGv_i32 a32, int index, MemOp opc);
109 TCGv_i32 a32, int index, MemOp opc);
111 TCGv_i32 a32, int index, MemOp opc);
113 TCGv_i32 a32, int index, MemOp opc);
115 int index, MemOp opc);
117 int index, MemOp opc);
119 int index, MemOp opc);
121 int index, MemOp opc);
H A Dtranslate.h719 static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp atom) in finalize_memop_atom() argument
721 if (s->align_mem && !(opc & MO_AMASK)) { in finalize_memop_atom()
722 opc |= MO_ALIGN; in finalize_memop_atom()
724 return opc | atom | s->be_data; in finalize_memop_atom()
734 static inline MemOp finalize_memop(DisasContext *s, MemOp opc) in finalize_memop() argument
737 return finalize_memop_atom(s, opc, atom); in finalize_memop()
748 static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc) in finalize_memop_pair() argument
751 return finalize_memop_atom(s, opc, atom); in finalize_memop_pair()
761 static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc) in finalize_memop_asimd() argument
772 if ((opc & MO_SIZE) == MO_128) { in finalize_memop_asimd()
[all …]
H A Dvfp.decode231 # We assemble bits 18 (op), 16 (u) and 7 (sx) into a single opc field
235 vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
237 vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
239 vd=%vd_dp imm=%vm_sp opc=%vcvt_fix_op
H A Dtranslate.c927 TCGv_i32 a32, int index, MemOp opc) in gen_aa32_ld_internal_i32() argument
929 TCGv addr = gen_aa32_addr(s, a32, opc); in gen_aa32_ld_internal_i32()
930 tcg_gen_qemu_ld_i32(val, addr, index, opc); in gen_aa32_ld_internal_i32()
934 TCGv_i32 a32, int index, MemOp opc) in gen_aa32_st_internal_i32() argument
936 TCGv addr = gen_aa32_addr(s, a32, opc); in gen_aa32_st_internal_i32()
937 tcg_gen_qemu_st_i32(val, addr, index, opc); in gen_aa32_st_internal_i32()
941 TCGv_i32 a32, int index, MemOp opc) in gen_aa32_ld_internal_i64() argument
943 TCGv addr = gen_aa32_addr(s, a32, opc); in gen_aa32_ld_internal_i64()
945 tcg_gen_qemu_ld_i64(val, addr, index, opc); in gen_aa32_ld_internal_i64()
948 if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { in gen_aa32_ld_internal_i64()
[all …]
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc549 encode_d_slot(LoongArchInsn opc, uint32_t d)
551 return opc | d;
555 encode_dj_slots(LoongArchInsn opc, uint32_t d, uint32_t j)
557 return opc | d | j << 5;
561 encode_djk_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k)
563 return opc | d | j << 5 | k << 10;
567 encode_djka_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k,
570 return opc | d | j << 5 | k << 10 | a << 15;
574 encode_djkm_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k,
577 return opc | d | j << 5 | k << 10 | m << 16;
[all …]
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc434 static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2)
436 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
446 static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm)
448 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm);
463 static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
465 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm);
482 static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
484 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm);
494 static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm)
496 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm);
[all …]
/openbmc/qemu/tcg/mips/
H A Dtcg-target.c.inc373 static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
378 inst = opc;
388 static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
393 inst = opc;
403 static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
408 inst = opc;
416 static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
421 opc = oph;
425 opc = opm;
428 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
[all …]
/openbmc/u-boot/common/
H A Dbedbug.c756 struct opcode *opc; in asmppc() local
776 if ((opc = find_opcode_by_name (scratch)) == (struct opcode *) 0) { in asmppc()
783 printf ("asmppc: Opcode = \"%s\"\n", opc->name); in asmppc()
787 if (opc->fields[i] == 0) in asmppc()
796 instr = opc->opcode; in asmppc()
801 oper[n_operands] = &operands[opc->fields[n_operands] - 1]; in asmppc()
823 if ((param = parse_operand (memaddr, opc, oper[n_operands], in asmppc()
855 int parse_operand (unsigned long memaddr, struct opcode *opc, in parse_operand() argument
869 if (opc->hint & H_RELATIVE) in parse_operand()
/openbmc/qemu/tcg/arm/
H A Dtcg-target.c.inc570 static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc,
573 tcg_out32(s, (cond << 28) | (0 << 25) | opc |
599 static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc,
602 tcg_out32(s, (cond << 28) | (1 << 25) | opc |
606 static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc,
609 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask);
614 static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt,
617 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24)
621 static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt,
629 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |
[all …]
/openbmc/qemu/tcg/i386/
H A Dtcg-target.c.inc574 static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
578 if (opc & P_GS) {
581 if (opc & P_DATA16) {
583 tcg_debug_assert((opc & P_REXW) == 0);
586 if (opc & P_SIMDF3) {
588 } else if (opc & P_SIMDF2) {
593 rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */
603 rex |= opc & (r >= 4 ? P_REXB_R : 0);
604 rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
610 if (opc & (P_EXT | P_EXT38 | P_EXT3A)) {
[all …]
/openbmc/qemu/tcg/tci/
H A Dtcg-target.c.inc574 TCGOpcode opc = (type == TCG_TYPE_I32
577 tcg_out_op_rrr(s, opc, a0, a1, a2);
588 TCGOpcode opc = (type == TCG_TYPE_I32
591 tcg_out_op_rrr(s, opc, a0, a1, a2);
613 TCGOpcode opc = (type == TCG_TYPE_I32
616 tcg_out_op_rrr(s, opc, a0, a1, a2);
631 TCGOpcode opc = (type == TCG_TYPE_I32
634 tcg_out_op_rrr(s, opc, a0, a1, a2);
764 TCGOpcode opc = (type == TCG_TYPE_I32
767 tcg_out_op_rrr(s, opc, a0, a1, a2);
[all …]
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.c.inc367 #define OPCD(opc) ((opc)<<26)
368 #define XO19(opc) (OPCD(19)|((opc)<<1))
369 #define MD30(opc) (OPCD(30)|((opc)<<2))
370 #define MDS30(opc) (OPCD(30)|((opc)<<1))
371 #define XO31(opc) (OPCD(31)|((opc)<<1))
372 #define XO58(opc) (OPCD(58)|(opc))
373 #define XO62(opc) (OPCD(62)|(opc))
374 #define VX4(opc) (OPCD(4)|(opc))
824 static void tcg_out_8ls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt,
830 i = opc | TAI(rt, ra, imm);
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dnanomips_translate.c.inc1109 static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
1119 switch (opc) {
1164 switch (opc) {
1196 switch (opc) {
1500 static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc,
1517 switch (opc) {
1541 static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
1550 switch (opc) {
1620 opc = extract32(ctx->opcode, 12, 2);
1621 gen_pool32axf_1_5_nanomips_insn(ctx, opc, ret, v1, v2);
[all …]
H A Dtranslate.c2049 static void gen_ld(DisasContext *ctx, uint32_t opc, in gen_ld() argument
2068 switch (opc) { in gen_ld()
2180 static void gen_st(DisasContext *ctx, uint32_t opc, int rt, in gen_st() argument
2189 switch (opc) { in gen_st()
2267 static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, in gen_flt_ldst() argument
2274 switch (opc) { in gen_flt_ldst()
2336 static void gen_arith_imm(DisasContext *ctx, uint32_t opc, in gen_arith_imm() argument
2341 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { in gen_arith_imm()
2348 switch (opc) { in gen_arith_imm()
2412 static void gen_logic_imm(DisasContext *ctx, uint32_t opc, in gen_logic_imm() argument
[all …]
/openbmc/qemu/hw/nvme/
H A Dnvme.h445 static inline const char *nvme_adm_opc_str(uint8_t opc) in nvme_adm_opc_str() argument
447 switch (opc) { in nvme_adm_opc_str()
468 static inline const char *nvme_io_opc_str(uint8_t opc) in nvme_io_opc_str() argument
470 switch (opc) { in nvme_io_opc_str()

123