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Searched refs:opc (Results 1 – 25 of 101) sorted by relevance

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/openbmc/qemu/include/hw/xtensa/
H A Dxtensa-isa.h378 xtensa_insnbuf slotbuf, xtensa_opcode opc);
383 const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc);
403 int xtensa_opcode_is_branch(xtensa_isa isa, xtensa_opcode opc);
405 int xtensa_opcode_is_jump(xtensa_isa isa, xtensa_opcode opc);
407 int xtensa_opcode_is_loop(xtensa_isa isa, xtensa_opcode opc);
409 int xtensa_opcode_is_call(xtensa_isa isa, xtensa_opcode opc);
418 int xtensa_opcode_num_operands(xtensa_isa isa, xtensa_opcode opc);
420 int xtensa_opcode_num_stateOperands(xtensa_isa isa, xtensa_opcode opc);
422 int xtensa_opcode_num_interfaceOperands(xtensa_isa isa, xtensa_opcode opc);
438 int xtensa_opcode_num_funcUnit_uses(xtensa_isa isa, xtensa_opcode opc);
[all …]
/openbmc/qemu/target/xtensa/
H A Dxtensa-isa.c662 xtensa_opcode opc; in xtensa_opcode_decode() local
669 opc = (intisa->slots[slot_id].opcode_decode_fn) (slotbuf); in xtensa_opcode_decode()
670 if (opc != XTENSA_UNDEFINED) { in xtensa_opcode_decode()
671 return opc; in xtensa_opcode_decode()
681 xtensa_insnbuf slotbuf, xtensa_opcode opc) in xtensa_opcode_encode() argument
689 CHECK_OPCODE(intisa, opc, -1); in xtensa_opcode_encode()
692 encode_fn = intisa->opcodes[opc].encode_fns[slot_id]; in xtensa_opcode_encode()
697 intisa->opcodes[opc].name, slot, intisa->formats[fmt].name); in xtensa_opcode_encode()
705 const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc) in xtensa_opcode_name() argument
709 CHECK_OPCODE(intisa, opc, NULL); in xtensa_opcode_name()
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/openbmc/qemu/disas/
H A Dxtensa.c81 xtensa_opcode opc; in print_insn_xtensa() local
88 opc = xtensa_opcode_decode(isa, fmt, slot, slotbuf); in print_insn_xtensa()
89 if (opc == XTENSA_UNDEFINED) { in print_insn_xtensa()
93 opnds = xtensa_opcode_num_operands(isa, opc); in print_insn_xtensa()
95 info->fprintf_func(info->stream, "%s", xtensa_opcode_name(isa, opc)); in print_insn_xtensa()
98 if (xtensa_operand_is_visible(isa, opc, opnd)) { in print_insn_xtensa()
103 xtensa_operand_get_field(isa, opc, opnd, fmt, slot, in print_insn_xtensa()
105 rc = xtensa_operand_decode(isa, opc, opnd, &v); in print_insn_xtensa()
108 } else if (xtensa_operand_is_register(isa, opc, opnd)) { in print_insn_xtensa()
109 xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd); in print_insn_xtensa()
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/openbmc/linux/drivers/spmi/
H A Dspmi-mtk-pmif.c289 static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) in pmif_arb_cmd() argument
296 if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) in pmif_arb_cmd()
299 cmd = opc - SPMI_CMD_RESET; in pmif_arb_cmd()
311 static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, in pmif_spmi_read_cmd() argument
332 if (opc >= 0x60 && opc <= 0x7f) in pmif_spmi_read_cmd()
333 opc = PMIF_CMD_REG; in pmif_spmi_read_cmd()
334 else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f)) in pmif_spmi_read_cmd()
335 opc = PMIF_CMD_EXT_REG_LONG; in pmif_spmi_read_cmd()
355 cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr; in pmif_spmi_read_cmd()
378 static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, in pmif_spmi_write_cmd() argument
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H A Dspmi-pmic-arb.c209 u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
210 int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
313 pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) in pmic_arb_non_data_cmd_v1() argument
326 cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20); in pmic_arb_non_data_cmd_v1()
338 pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid) in pmic_arb_non_data_cmd_v2() argument
344 static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) in pmic_arb_cmd() argument
348 dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid); in pmic_arb_cmd()
351 if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) in pmic_arb_cmd()
354 return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid); in pmic_arb_cmd()
357 static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, u8 sid, in pmic_arb_fmt_read_cmd() argument
[all …]
H A Dhisi-spmi-controller.c112 u8 opc, u8 slave_id, u16 slave_addr, u8 *__buf, size_t bc) in spmi_read_cmd() argument
129 switch (opc) { in spmi_read_cmd()
140 dev_err(&ctrl->dev, "invalid read cmd 0x%x\n", opc); in spmi_read_cmd()
179 opc, slave_id, slave_addr, bc + 1); in spmi_read_cmd()
188 u8 opc, u8 slave_id, u16 slave_addr, const u8 *__buf, size_t bc) in spmi_write_cmd() argument
205 switch (opc) { in spmi_write_cmd()
216 dev_err(&ctrl->dev, "invalid write cmd 0x%x\n", opc); in spmi_write_cmd()
255 opc, slave_id, slave_addr, bc); in spmi_write_cmd()
/openbmc/linux/drivers/misc/sgi-gru/
H A Dgruhandles.c65 static int wait_instruction_complete(void *h, enum mcs_op opc) in wait_instruction_complete() argument
81 update_mcs_stats(opc, get_cycles() - start_time); in wait_instruction_complete()
89 cch->opc = CCHOP_ALLOCATE; in cch_allocate()
103 cch->opc = CCHOP_START; in cch_start()
110 cch->opc = CCHOP_INTERRUPT; in cch_interrupt()
119 cch->opc = CCHOP_DEALLOCATE; in cch_deallocate()
134 cch->opc = CCHOP_INTERRUPT_SYNC; in cch_interrupt_sync()
151 tgh->opc = TGHOP_TLBINV; in tgh_invalidate()
167 tfh->opc = TFHOP_WRITE_ONLY; in tfh_write_only()
183 tfh->opc = TFHOP_WRITE_RESTART; in tfh_write_restart()
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/openbmc/linux/arch/s390/include/asm/
H A Dcpacf.h176 static __always_inline void __cpacf_query_rre(u32 opc, u8 r1, u8 r2, in __cpacf_query_rre() argument
184 : [opc] "i" (opc), in __cpacf_query_rre()
189 static __always_inline void __cpacf_query_rrf(u32 opc, in __cpacf_query_rrf() argument
198 : [opc] "i" (opc), [r1] "i" (r1), [r2] "i" (r2), in __cpacf_query_rrf()
337 [opc] "i" (CPACF_KM) in cpacf_km()
369 [opc] "i" (CPACF_KMC) in cpacf_kmc()
397 [opc] "i" (CPACF_KIMD) in cpacf_kimd()
422 [opc] "i" (CPACF_KLMD) in cpacf_klmd()
450 [opc] "i" (CPACF_KMAC) in cpacf_kmac()
485 [opc] "i" (CPACF_KMCTR) in cpacf_kmctr()
[all …]
/openbmc/qemu/tcg/
H A Dtcg-op-vec.c68 TCGOpcode opc = *list; in tcg_can_emit_vecop_list() local
71 switch (opc) { in tcg_can_emit_vecop_list()
91 if (tcg_can_emit_vec_op(opc, type, vece)) { in tcg_can_emit_vecop_list()
100 switch (opc) { in tcg_can_emit_vecop_list()
143 void vec_gen_2(TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, TCGArg a) in vec_gen_2() argument
145 TCGOp *op = tcg_emit_op(opc, 2); in vec_gen_2()
152 void vec_gen_3(TCGOpcode opc, TCGType type, unsigned vece, in vec_gen_3() argument
155 TCGOp *op = tcg_emit_op(opc, 3); in vec_gen_3()
163 void vec_gen_4(TCGOpcode opc, TCGType type, unsigned vece, in vec_gen_4() argument
166 TCGOp *op = tcg_emit_op(opc, 4); in vec_gen_4()
[all …]
H A Dtcg-op-ldst.c90 static void gen_ldst(TCGOpcode opc, TCGTemp *vl, TCGTemp *vh, in gen_ldst() argument
95 tcg_gen_op4(opc, temp_arg(vl), temp_arg(vh), temp_arg(addr), oi); in gen_ldst()
97 tcg_gen_op3(opc, temp_arg(vl), temp_arg(addr), oi); in gen_ldst()
105 tcg_gen_op5(opc, temp_arg(vl), temp_arg(vh), in gen_ldst()
108 tcg_gen_op4(opc, temp_arg(vl), temp_arg(al), temp_arg(ah), oi); in gen_ldst()
113 static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 v, TCGTemp *addr, MemOpIdx oi) in gen_ldst_i64() argument
118 gen_ldst(opc, vl, vh, addr, oi); in gen_ldst_i64()
120 gen_ldst(opc, tcgv_i64_temp(v), NULL, addr, oi); in gen_ldst_i64()
232 TCGOpcode opc; in tcg_gen_qemu_ld_i32_int() local
249 opc = INDEX_op_qemu_ld_a32_i32; in tcg_gen_qemu_ld_i32_int()
[all …]
H A Doptimize.c407 op->opc = new_op; in tcg_opt_gen_mov()
969 const TCGOpDef *def = &tcg_op_defs[op->opc]; in finish_folding()
1017 t = do_constant_folding(op->opc, ctx->type, t, 0); in fold_const1()
1029 t1 = do_constant_folding(op->opc, ctx->type, t1, t2); in fold_const2()
1107 op->opc = not_op; in fold_to_not()
1264 op->opc = (ctx->type == TCG_TYPE_I32 in fold_addsub2()
1352 op->opc = INDEX_op_br; in fold_brcond()
1425 op->opc = INDEX_op_brcond_i32; in fold_brcond2()
1432 op->opc = INDEX_op_brcond_i32; in fold_brcond2()
1444 op->opc = INDEX_op_br; in fold_brcond2()
[all …]
H A Dtcg-op.c40 TCGOp * NI tcg_gen_op1(TCGOpcode opc, TCGArg a1) in tcg_gen_op1() argument
42 TCGOp *op = tcg_emit_op(opc, 1); in tcg_gen_op1()
47 TCGOp * NI tcg_gen_op2(TCGOpcode opc, TCGArg a1, TCGArg a2) in tcg_gen_op2() argument
49 TCGOp *op = tcg_emit_op(opc, 2); in tcg_gen_op2()
55 TCGOp * NI tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3) in tcg_gen_op3() argument
57 TCGOp *op = tcg_emit_op(opc, 3); in tcg_gen_op3()
64 TCGOp * NI tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, in tcg_gen_op4() argument
67 TCGOp *op = tcg_emit_op(opc, 4); in tcg_gen_op4()
75 TCGOp * NI tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, in tcg_gen_op5() argument
78 TCGOp *op = tcg_emit_op(opc, 5); in tcg_gen_op5()
[all …]
/openbmc/linux/arch/mips/mm/
H A Duasm-micromips.c156 static void build_insn(u32 **buf, enum opcode opc, ...) in build_insn() argument
162 if (opc < 0 || opc >= insn_invalid || in build_insn()
163 (opc == insn_daddiu && r4k_daddiu_bug()) || in build_insn()
164 (insn_table_MM[opc].match == 0 && insn_table_MM[opc].fields == 0)) in build_insn()
165 panic("Unsupported Micro-assembler instruction %d", opc); in build_insn()
167 ip = &insn_table_MM[opc]; in build_insn()
170 va_start(ap, opc); in build_insn()
172 if (opc == insn_mfc0 || opc == insn_mtc0 || in build_insn()
173 opc == insn_cfc1 || opc == insn_ctc1) in build_insn()
179 if (opc == insn_mfc0 || opc == insn_mtc0 || in build_insn()
[all …]
H A Duasm-mips.c232 static void build_insn(u32 **buf, enum opcode opc, ...) in build_insn() argument
238 if (opc < 0 || opc >= insn_invalid || in build_insn()
239 (opc == insn_daddiu && r4k_daddiu_bug()) || in build_insn()
240 (insn_table[opc].match == 0 && insn_table[opc].fields == 0)) in build_insn()
241 panic("Unsupported Micro-assembler instruction %d", opc); in build_insn()
243 ip = &insn_table[opc]; in build_insn()
246 va_start(ap, opc); in build_insn()
/openbmc/u-boot/drivers/mmc/
H A Dsh_mmcif.c337 u32 opc = cmd->cmdidx; in sh_mmcif_set_cmd() local
358 if (opc == MMC_CMD_SWITCH) in sh_mmcif_set_cmd()
380 if (opc == MMC_CMD_WRITE_SINGLE_BLOCK || in sh_mmcif_set_cmd()
381 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) in sh_mmcif_set_cmd()
384 if (opc == MMC_CMD_READ_MULTIPLE_BLOCK || in sh_mmcif_set_cmd()
385 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) { in sh_mmcif_set_cmd()
390 if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID || in sh_mmcif_set_cmd()
391 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID) in sh_mmcif_set_cmd()
394 if (opc == MMC_CMD_SEND_OP_COND) in sh_mmcif_set_cmd()
397 if (opc == MMC_CMD_ALL_SEND_CID || in sh_mmcif_set_cmd()
[all …]
H A Dsh_sdhi.c477 struct mmc_data *data, unsigned short opc) in sh_sdhi_set_cmd() argument
482 return opc | BIT(6); in sh_sdhi_set_cmd()
485 switch (opc) { in sh_sdhi_set_cmd()
487 return opc | (data ? 0x1c00 : 0x40); in sh_sdhi_set_cmd()
489 return opc | (data ? 0x1c00 : 0); in sh_sdhi_set_cmd()
491 return opc | 0x0700; in sh_sdhi_set_cmd()
495 return opc; in sh_sdhi_set_cmd()
500 struct mmc_data *data, unsigned short opc) in sh_sdhi_data_trans() argument
504 switch (opc) { in sh_sdhi_data_trans()
510 opc); in sh_sdhi_data_trans()
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/openbmc/linux/drivers/scsi/pm8001/
H A Dpm80xx_tracepoints.h79 TP_PROTO(u32 id, u32 opc, u32 htag, u32 qi, u32 pi, u32 ci),
81 TP_ARGS(id, opc, htag, qi, pi, ci),
85 __field(u32, opc)
94 __entry->opc = opc;
102 __entry->id, __entry->opc, __entry->htag, __entry->qi,
/openbmc/qemu/target/arm/tcg/
H A Dtranslate-a32.h107 TCGv_i32 a32, int index, MemOp opc);
109 TCGv_i32 a32, int index, MemOp opc);
111 TCGv_i32 a32, int index, MemOp opc);
113 TCGv_i32 a32, int index, MemOp opc);
115 int index, MemOp opc);
117 int index, MemOp opc);
119 int index, MemOp opc);
121 int index, MemOp opc);
/openbmc/openbmc/poky/meta/recipes-devtools/binutils/binutils/
H A D0007-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch13 opcodes/ppc-opc.c | 4 +---
16 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
18 --- a/opcodes/ppc-opc.c
19 +++ b/opcodes/ppc-opc.c
/openbmc/linux/arch/mips/kvm/
H A Dvz.c651 u32 *opc; in is_eva_am_mapped() local
665 opc = (u32 *)vcpu->arch.pc; in is_eva_am_mapped()
667 opc += 1; in is_eva_am_mapped()
668 err = kvm_get_badinstr(opc, vcpu, &inst.word); in is_eva_am_mapped()
819 u32 *opc = (u32 *) vcpu->arch.pc; in kvm_trap_vz_no_handler() local
829 opc += 1; in kvm_trap_vz_no_handler()
830 kvm_get_badinstr(opc, vcpu, &inst); in kvm_trap_vz_no_handler()
833 exccode, opc, inst, badvaddr, in kvm_trap_vz_no_handler()
876 u32 *opc, u32 cause, in kvm_vz_gpsi_cop0() argument
1075 u32 *opc, u32 cause, in kvm_vz_gpsi_cache() argument
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/openbmc/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc549 encode_d_slot(LoongArchInsn opc, uint32_t d)
551 return opc | d;
555 encode_dj_slots(LoongArchInsn opc, uint32_t d, uint32_t j)
557 return opc | d | j << 5;
561 encode_djk_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k)
563 return opc | d | j << 5 | k << 10;
567 encode_djka_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k,
570 return opc | d | j << 5 | k << 10 | a << 15;
574 encode_djkm_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k,
577 return opc | d | j << 5 | k << 10 | m << 16;
[all …]
/openbmc/qemu/tcg/tci/
H A Dtcg-target.c.inc698 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
704 switch (opc) {
706 tcg_out_op_r(s, opc, args[0]);
710 tcg_out_op_l(s, opc, arg_label(args[0]));
714 tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]);
719 tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2],
736 tcg_out_ldst(s, opc, args[0], args[1], args[2]);
761 tcg_out_op_rrr(s, opc, args[0], args[1], args[2]);
767 TCGArg max = opc == INDEX_op_deposit_i32 ? 32 : 64;
772 tcg_out_op_rrrbb(s, opc, args[0], args[1], args[2], pos, len);
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/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc447 static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2)
449 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
459 static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm)
461 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm);
476 static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
478 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm);
495 static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
497 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm);
507 static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm)
509 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm);
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/openbmc/qemu/tcg/arm/
H A Dtcg-target.c.inc562 static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc,
565 tcg_out32(s, (cond << 28) | (0 << 25) | opc |
591 static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc,
594 tcg_out32(s, (cond << 28) | (1 << 25) | opc |
598 static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc,
601 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask);
606 static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt,
609 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24)
613 static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt,
621 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsh_mmcif.c807 u32 opc = cmd->opcode; in sh_mmcif_set_cmd() local
861 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) in sh_mmcif_set_cmd()
864 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { in sh_mmcif_set_cmd()
870 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || in sh_mmcif_set_cmd()
871 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) in sh_mmcif_set_cmd()
874 if (opc == MMC_SEND_OP_COND) in sh_mmcif_set_cmd()
877 if (opc == MMC_ALL_SEND_CID || in sh_mmcif_set_cmd()
878 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) in sh_mmcif_set_cmd()
881 return (opc << 24) | tmp; in sh_mmcif_set_cmd()
885 struct mmc_request *mrq, u32 opc) in sh_mmcif_data_trans() argument
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