1*f0984d40SFabiano Rosas# AArch32 VFP instruction descriptions (conditional insns) 2*f0984d40SFabiano Rosas# 3*f0984d40SFabiano Rosas# Copyright (c) 2019 Linaro, Ltd 4*f0984d40SFabiano Rosas# 5*f0984d40SFabiano Rosas# This library is free software; you can redistribute it and/or 6*f0984d40SFabiano Rosas# modify it under the terms of the GNU Lesser General Public 7*f0984d40SFabiano Rosas# License as published by the Free Software Foundation; either 8*f0984d40SFabiano Rosas# version 2.1 of the License, or (at your option) any later version. 9*f0984d40SFabiano Rosas# 10*f0984d40SFabiano Rosas# This library is distributed in the hope that it will be useful, 11*f0984d40SFabiano Rosas# but WITHOUT ANY WARRANTY; without even the implied warranty of 12*f0984d40SFabiano Rosas# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13*f0984d40SFabiano Rosas# Lesser General Public License for more details. 14*f0984d40SFabiano Rosas# 15*f0984d40SFabiano Rosas# You should have received a copy of the GNU Lesser General Public 16*f0984d40SFabiano Rosas# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17*f0984d40SFabiano Rosas 18*f0984d40SFabiano Rosas# 19*f0984d40SFabiano Rosas# This file is processed by scripts/decodetree.py 20*f0984d40SFabiano Rosas# 21*f0984d40SFabiano Rosas# Encodings for the conditional VFP instructions are here: 22*f0984d40SFabiano Rosas# generally anything matching A32 23*f0984d40SFabiano Rosas# cccc 11.. .... .... .... 101. .... .... 24*f0984d40SFabiano Rosas# and T32 25*f0984d40SFabiano Rosas# 1110 110. .... .... .... 101. .... .... 26*f0984d40SFabiano Rosas# 1110 1110 .... .... .... 101. .... .... 27*f0984d40SFabiano Rosas# (but those patterns might also cover some Neon instructions, 28*f0984d40SFabiano Rosas# which do not live in this file.) 29*f0984d40SFabiano Rosas 30*f0984d40SFabiano Rosas# VFP registers have an odd encoding with a four-bit field 31*f0984d40SFabiano Rosas# and a one-bit field which are assembled in different orders 32*f0984d40SFabiano Rosas# depending on whether the register is double or single precision. 33*f0984d40SFabiano Rosas# Each individual instruction function must do the checks for 34*f0984d40SFabiano Rosas# "double register selected but CPU does not have double support" 35*f0984d40SFabiano Rosas# and "double register number has bit 4 set but CPU does not 36*f0984d40SFabiano Rosas# support D16-D31" (which should UNDEF). 37*f0984d40SFabiano Rosas%vm_dp 5:1 0:4 38*f0984d40SFabiano Rosas%vm_sp 0:4 5:1 39*f0984d40SFabiano Rosas%vn_dp 7:1 16:4 40*f0984d40SFabiano Rosas%vn_sp 16:4 7:1 41*f0984d40SFabiano Rosas%vd_dp 22:1 12:4 42*f0984d40SFabiano Rosas%vd_sp 12:4 22:1 43*f0984d40SFabiano Rosas 44*f0984d40SFabiano Rosas%vmov_idx_b 21:1 5:2 45*f0984d40SFabiano Rosas%vmov_idx_h 21:1 6:1 46*f0984d40SFabiano Rosas 47*f0984d40SFabiano Rosas%vmov_imm 16:4 0:4 48*f0984d40SFabiano Rosas 49*f0984d40SFabiano Rosas@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp 50*f0984d40SFabiano Rosas@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp 51*f0984d40SFabiano Rosas 52*f0984d40SFabiano Rosas@vfp_dm_ss ................................ vm=%vm_sp vd=%vd_sp 53*f0984d40SFabiano Rosas@vfp_dm_dd ................................ vm=%vm_dp vd=%vd_dp 54*f0984d40SFabiano Rosas@vfp_dm_ds ................................ vm=%vm_sp vd=%vd_dp 55*f0984d40SFabiano Rosas@vfp_dm_sd ................................ vm=%vm_dp vd=%vd_sp 56*f0984d40SFabiano Rosas 57*f0984d40SFabiano Rosas# VMOV scalar to general-purpose register; note that this does 58*f0984d40SFabiano Rosas# include some Neon cases. 59*f0984d40SFabiano RosasVMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \ 60*f0984d40SFabiano Rosas vn=%vn_dp size=0 index=%vmov_idx_b 61*f0984d40SFabiano RosasVMOV_to_gp ---- 1110 u:1 0. 1 .... rt:4 1011 ..1 1 0000 \ 62*f0984d40SFabiano Rosas vn=%vn_dp size=1 index=%vmov_idx_h 63*f0984d40SFabiano RosasVMOV_to_gp ---- 1110 0 0 index:1 1 .... rt:4 1011 .00 1 0000 \ 64*f0984d40SFabiano Rosas vn=%vn_dp size=2 u=0 65*f0984d40SFabiano Rosas 66*f0984d40SFabiano RosasVMOV_from_gp ---- 1110 0 1. 0 .... rt:4 1011 ... 1 0000 \ 67*f0984d40SFabiano Rosas vn=%vn_dp size=0 index=%vmov_idx_b 68*f0984d40SFabiano RosasVMOV_from_gp ---- 1110 0 0. 0 .... rt:4 1011 ..1 1 0000 \ 69*f0984d40SFabiano Rosas vn=%vn_dp size=1 index=%vmov_idx_h 70*f0984d40SFabiano RosasVMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1 0000 \ 71*f0984d40SFabiano Rosas vn=%vn_dp size=2 72*f0984d40SFabiano Rosas 73*f0984d40SFabiano RosasVDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \ 74*f0984d40SFabiano Rosas vn=%vn_dp 75*f0984d40SFabiano Rosas 76*f0984d40SFabiano RosasVMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000 77*f0984d40SFabiano RosasVMOV_half ---- 1110 000 l:1 .... rt:4 1001 . 001 0000 vn=%vn_sp 78*f0984d40SFabiano RosasVMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp 79*f0984d40SFabiano Rosas 80*f0984d40SFabiano RosasVMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp 81*f0984d40SFabiano RosasVMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp 82*f0984d40SFabiano Rosas 83*f0984d40SFabiano RosasVLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp 84*f0984d40SFabiano RosasVLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp 85*f0984d40SFabiano RosasVLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp 86*f0984d40SFabiano Rosas 87*f0984d40SFabiano Rosas# We split the load/store multiple up into two patterns to avoid 88*f0984d40SFabiano Rosas# overlap with other insns in the "Advanced SIMD load/store and 64-bit move" 89*f0984d40SFabiano Rosas# grouping: 90*f0984d40SFabiano Rosas# P=0 U=0 W=0 is 64-bit VMOV 91*f0984d40SFabiano Rosas# P=1 W=0 is VLDR/VSTR 92*f0984d40SFabiano Rosas# P=U W=1 is UNDEF 93*f0984d40SFabiano Rosas# leaving P=0 U=1 W=x and P=1 U=0 W=1 for load/store multiple. 94*f0984d40SFabiano Rosas# These include FSTM/FLDM. 95*f0984d40SFabiano RosasVLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \ 96*f0984d40SFabiano Rosas vd=%vd_sp p=0 u=1 97*f0984d40SFabiano RosasVLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \ 98*f0984d40SFabiano Rosas vd=%vd_dp p=0 u=1 99*f0984d40SFabiano Rosas 100*f0984d40SFabiano RosasVLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \ 101*f0984d40SFabiano Rosas vd=%vd_sp p=1 u=0 w=1 102*f0984d40SFabiano RosasVLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \ 103*f0984d40SFabiano Rosas vd=%vd_dp p=1 u=0 w=1 104*f0984d40SFabiano Rosas 105*f0984d40SFabiano Rosas# 3-register VFP data-processing; bits [23,21:20,6] identify the operation. 106*f0984d40SFabiano RosasVMLA_hp ---- 1110 0.00 .... .... 1001 .0.0 .... @vfp_dnm_s 107*f0984d40SFabiano RosasVMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s 108*f0984d40SFabiano RosasVMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d 109*f0984d40SFabiano Rosas 110*f0984d40SFabiano RosasVMLS_hp ---- 1110 0.00 .... .... 1001 .1.0 .... @vfp_dnm_s 111*f0984d40SFabiano RosasVMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s 112*f0984d40SFabiano RosasVMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d 113*f0984d40SFabiano Rosas 114*f0984d40SFabiano RosasVNMLS_hp ---- 1110 0.01 .... .... 1001 .0.0 .... @vfp_dnm_s 115*f0984d40SFabiano RosasVNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s 116*f0984d40SFabiano RosasVNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d 117*f0984d40SFabiano Rosas 118*f0984d40SFabiano RosasVNMLA_hp ---- 1110 0.01 .... .... 1001 .1.0 .... @vfp_dnm_s 119*f0984d40SFabiano RosasVNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s 120*f0984d40SFabiano RosasVNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d 121*f0984d40SFabiano Rosas 122*f0984d40SFabiano RosasVMUL_hp ---- 1110 0.10 .... .... 1001 .0.0 .... @vfp_dnm_s 123*f0984d40SFabiano RosasVMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s 124*f0984d40SFabiano RosasVMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d 125*f0984d40SFabiano Rosas 126*f0984d40SFabiano RosasVNMUL_hp ---- 1110 0.10 .... .... 1001 .1.0 .... @vfp_dnm_s 127*f0984d40SFabiano RosasVNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s 128*f0984d40SFabiano RosasVNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d 129*f0984d40SFabiano Rosas 130*f0984d40SFabiano RosasVADD_hp ---- 1110 0.11 .... .... 1001 .0.0 .... @vfp_dnm_s 131*f0984d40SFabiano RosasVADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s 132*f0984d40SFabiano RosasVADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d 133*f0984d40SFabiano Rosas 134*f0984d40SFabiano RosasVSUB_hp ---- 1110 0.11 .... .... 1001 .1.0 .... @vfp_dnm_s 135*f0984d40SFabiano RosasVSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s 136*f0984d40SFabiano RosasVSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d 137*f0984d40SFabiano Rosas 138*f0984d40SFabiano RosasVDIV_hp ---- 1110 1.00 .... .... 1001 .0.0 .... @vfp_dnm_s 139*f0984d40SFabiano RosasVDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s 140*f0984d40SFabiano RosasVDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d 141*f0984d40SFabiano Rosas 142*f0984d40SFabiano RosasVFMA_hp ---- 1110 1.10 .... .... 1001 .0. 0 .... @vfp_dnm_s 143*f0984d40SFabiano RosasVFMS_hp ---- 1110 1.10 .... .... 1001 .1. 0 .... @vfp_dnm_s 144*f0984d40SFabiano RosasVFNMA_hp ---- 1110 1.01 .... .... 1001 .0. 0 .... @vfp_dnm_s 145*f0984d40SFabiano RosasVFNMS_hp ---- 1110 1.01 .... .... 1001 .1. 0 .... @vfp_dnm_s 146*f0984d40SFabiano Rosas 147*f0984d40SFabiano RosasVFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s 148*f0984d40SFabiano RosasVFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s 149*f0984d40SFabiano RosasVFNMA_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s 150*f0984d40SFabiano RosasVFNMS_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s 151*f0984d40SFabiano Rosas 152*f0984d40SFabiano RosasVFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d 153*f0984d40SFabiano RosasVFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d 154*f0984d40SFabiano RosasVFNMA_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d 155*f0984d40SFabiano RosasVFNMS_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d 156*f0984d40SFabiano Rosas 157*f0984d40SFabiano RosasVMOV_imm_hp ---- 1110 1.11 .... .... 1001 0000 .... \ 158*f0984d40SFabiano Rosas vd=%vd_sp imm=%vmov_imm 159*f0984d40SFabiano RosasVMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \ 160*f0984d40SFabiano Rosas vd=%vd_sp imm=%vmov_imm 161*f0984d40SFabiano RosasVMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \ 162*f0984d40SFabiano Rosas vd=%vd_dp imm=%vmov_imm 163*f0984d40SFabiano Rosas 164*f0984d40SFabiano RosasVMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss 165*f0984d40SFabiano RosasVMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd 166*f0984d40SFabiano Rosas 167*f0984d40SFabiano RosasVABS_hp ---- 1110 1.11 0000 .... 1001 11.0 .... @vfp_dm_ss 168*f0984d40SFabiano RosasVABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss 169*f0984d40SFabiano RosasVABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd 170*f0984d40SFabiano Rosas 171*f0984d40SFabiano RosasVNEG_hp ---- 1110 1.11 0001 .... 1001 01.0 .... @vfp_dm_ss 172*f0984d40SFabiano RosasVNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss 173*f0984d40SFabiano RosasVNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd 174*f0984d40SFabiano Rosas 175*f0984d40SFabiano RosasVSQRT_hp ---- 1110 1.11 0001 .... 1001 11.0 .... @vfp_dm_ss 176*f0984d40SFabiano RosasVSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss 177*f0984d40SFabiano RosasVSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd 178*f0984d40SFabiano Rosas 179*f0984d40SFabiano RosasVCMP_hp ---- 1110 1.11 010 z:1 .... 1001 e:1 1.0 .... \ 180*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 181*f0984d40SFabiano RosasVCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \ 182*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 183*f0984d40SFabiano RosasVCMP_dp ---- 1110 1.11 010 z:1 .... 1011 e:1 1.0 .... \ 184*f0984d40SFabiano Rosas vd=%vd_dp vm=%vm_dp 185*f0984d40SFabiano Rosas 186*f0984d40SFabiano Rosas# VCVTT and VCVTB from f16: Vd format depends on size bit; Vm is always vm_sp 187*f0984d40SFabiano RosasVCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \ 188*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 189*f0984d40SFabiano RosasVCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \ 190*f0984d40SFabiano Rosas vd=%vd_dp vm=%vm_sp 191*f0984d40SFabiano Rosas 192*f0984d40SFabiano Rosas# VCVTB and VCVTT to f16: Vd format is always vd_sp; 193*f0984d40SFabiano Rosas# Vm format depends on size bit 194*f0984d40SFabiano RosasVCVT_b16_f32 ---- 1110 1.11 0011 .... 1001 t:1 1.0 .... \ 195*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 196*f0984d40SFabiano RosasVCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \ 197*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 198*f0984d40SFabiano RosasVCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \ 199*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_dp 200*f0984d40SFabiano Rosas 201*f0984d40SFabiano RosasVRINTR_hp ---- 1110 1.11 0110 .... 1001 01.0 .... @vfp_dm_ss 202*f0984d40SFabiano RosasVRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss 203*f0984d40SFabiano RosasVRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd 204*f0984d40SFabiano Rosas 205*f0984d40SFabiano RosasVRINTZ_hp ---- 1110 1.11 0110 .... 1001 11.0 .... @vfp_dm_ss 206*f0984d40SFabiano RosasVRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss 207*f0984d40SFabiano RosasVRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd 208*f0984d40SFabiano Rosas 209*f0984d40SFabiano RosasVRINTX_hp ---- 1110 1.11 0111 .... 1001 01.0 .... @vfp_dm_ss 210*f0984d40SFabiano RosasVRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss 211*f0984d40SFabiano RosasVRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd 212*f0984d40SFabiano Rosas 213*f0984d40SFabiano Rosas# VCVT between single and double: 214*f0984d40SFabiano Rosas# Vm precision depends on size; Vd is its reverse 215*f0984d40SFabiano RosasVCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds 216*f0984d40SFabiano RosasVCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd 217*f0984d40SFabiano Rosas 218*f0984d40SFabiano Rosas# VCVT from integer to floating point: Vm always single; Vd depends on size 219*f0984d40SFabiano RosasVCVT_int_hp ---- 1110 1.11 1000 .... 1001 s:1 1.0 .... \ 220*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 221*f0984d40SFabiano RosasVCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \ 222*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 223*f0984d40SFabiano RosasVCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \ 224*f0984d40SFabiano Rosas vd=%vd_dp vm=%vm_sp 225*f0984d40SFabiano Rosas 226*f0984d40SFabiano Rosas# VJCVT is always dp to sp 227*f0984d40SFabiano RosasVJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd 228*f0984d40SFabiano Rosas 229*f0984d40SFabiano Rosas# VCVT between floating-point and fixed-point. The immediate value 230*f0984d40SFabiano Rosas# is in the same format as a Vm single-precision register number. 231*f0984d40SFabiano Rosas# We assemble bits 18 (op), 16 (u) and 7 (sx) into a single opc field 232*f0984d40SFabiano Rosas# for the convenience of the trans_VCVT_fix functions. 233*f0984d40SFabiano Rosas%vcvt_fix_op 18:1 16:1 7:1 234*f0984d40SFabiano RosasVCVT_fix_hp ---- 1110 1.11 1.1. .... 1001 .1.0 .... \ 235*f0984d40SFabiano Rosas vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op 236*f0984d40SFabiano RosasVCVT_fix_sp ---- 1110 1.11 1.1. .... 1010 .1.0 .... \ 237*f0984d40SFabiano Rosas vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op 238*f0984d40SFabiano RosasVCVT_fix_dp ---- 1110 1.11 1.1. .... 1011 .1.0 .... \ 239*f0984d40SFabiano Rosas vd=%vd_dp imm=%vm_sp opc=%vcvt_fix_op 240*f0984d40SFabiano Rosas 241*f0984d40SFabiano Rosas# VCVT float to integer (VCVT and VCVTR): Vd always single; Vd depends on size 242*f0984d40SFabiano RosasVCVT_hp_int ---- 1110 1.11 110 s:1 .... 1001 rz:1 1.0 .... \ 243*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 244*f0984d40SFabiano RosasVCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \ 245*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 246*f0984d40SFabiano RosasVCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ 247*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_dp 248