Searched refs:num_vcn_inst (Results 1 – 17 of 17) sorted by relevance
86 adev->vcn.num_vcn_inst = 2; in vcn_v2_5_early_init()93 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_early_init()127 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()161 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()260 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_sw_fini()298 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_hw_init()349 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_hw_fini()420 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_mc_resume()577 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_disable_clock_gating()742 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_enable_clock_gating()[all …]
109 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_3_sw_init()175 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_3_sw_fini()215 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_hw_init()223 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_hw_init()882 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_3_start_sriov()1052 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_start()1256 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_stop()1446 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_set_unified_ring_funcs()1603 if (inst >= adev->vcn.num_vcn_inst) { in vcn_v4_0_3_process_interrupt()1705 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in vcn_v4_0_3_query_ras_error_count()[all …]
85 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_early_init()126 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_sw_init()214 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_sw_fini()258 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_init()270 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_init()308 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_fini()1051 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_start()1258 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_start_sriov()1464 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_stop()1848 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_set_unified_ring_funcs()[all …]
153 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_init()263 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_fini()307 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_init()338 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_init()382 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_fini()1104 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_start()1322 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_start_sriov()1527 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_stop()2030 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_set_dec_ring_funcs()2048 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_set_enc_ring_funcs()[all …]
113 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in amdgpu_vcn_sw_init()185 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_sw_init()234 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in amdgpu_vcn_sw_fini()304 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_vcn_suspend()331 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_vcn_resume()376 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in amdgpu_vcn_idle_work_handler()1042 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_setup_ucode()1207 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_ras_late_init()
66 return (adev->xcp_mgr->num_xcps > adev->vcn.num_vcn_inst); in aqua_vanjaram_xcp_vcn_shared()353 num_vcn = adev->vcn.num_vcn_inst; in __aqua_vanjaram_get_xcp_ip_info()653 adev->vcn.num_vcn_inst = hweight32(adev->vcn.inst_mask); in aqua_vanjaram_init_soc_config()
1273 if (adev->vcn.num_vcn_inst < in amdgpu_discovery_reg_base_init()1275 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = in amdgpu_discovery_reg_base_init()1277 adev->vcn.num_vcn_inst++; in amdgpu_discovery_reg_base_init()1284 adev->vcn.num_vcn_inst + 1, in amdgpu_discovery_reg_base_init()1397 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { in amdgpu_discovery_harvest_ip()1586 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { in amdgpu_discovery_get_vcn_info()1604 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { in amdgpu_discovery_get_vcn_info()2206 adev->vcn.num_vcn_inst = 1; in amdgpu_discovery_set_ip_blocks()2268 adev->vcn.num_vcn_inst = 2; in amdgpu_discovery_set_ip_blocks()2296 adev->vcn.num_vcn_inst = 2; in amdgpu_discovery_set_ip_blocks()
269 uint8_t num_vcn_inst; member
153 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in soc21_query_video_codecs()
434 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()446 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()
214 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in nv_query_video_codecs()
306 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in jpeg_v4_0_3_hw_init()
2163 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_debugfs_init()
361 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0); in amdgpu_ras_instance_mask_check()
1830 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_v13_0_set_performance_level()1845 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_v13_0_set_performance_level()2070 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_v13_0_set_vcn_enable()
2074 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) in default_attr_update()2089 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) in default_attr_update()
1016 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in sienna_cichlid_set_default_dpm_table()1039 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in sienna_cichlid_set_default_dpm_table()1140 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in sienna_cichlid_dpm_set_vcn_enable()