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Searched refs:mul (Results 1 – 25 of 69) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-at91/arm920t/
H A Dclock.c43 unsigned i, div = 0, mul = 0, diff = 1 << 30; in at91_pll_calc() local
77 mul = mul1; in at91_pll_calc()
84 return ret | ((mul - 1) << 16) | div; in at91_pll_calc()
92 unsigned mul, div; in at91_pll_rate() local
95 mul = (reg >> 16) & 0x7ff; in at91_pll_rate()
96 if (div && mul) { in at91_pll_rate()
98 freq *= mul + 1; in at91_pll_rate()
/openbmc/u-boot/include/linux/
H A Dmath64.h150 static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift) in mul_u64_u32_shr() argument
152 return (u64)(((unsigned __int128)a * mul) >> shift); in mul_u64_u32_shr()
157 static inline u64 mul_u64_u64_shr(u64 a, u64 mul, unsigned int shift) in mul_u64_u64_shr() argument
159 return (u64)(((unsigned __int128)a * mul) >> shift); in mul_u64_u64_shr()
166 static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift) in mul_u64_u32_shr() argument
174 ret = mul_u32_u32(al, mul) >> shift; in mul_u64_u32_shr()
176 ret += mul_u32_u32(ah, mul) << (32 - shift); in mul_u64_u32_shr()
229 static inline u64 mul_u64_u32_div(u64 a, u32 mul, u32 divisor) in mul_u64_u32_div() argument
243 rl.ll = mul_u32_u32(u.l.low, mul); in mul_u64_u32_div()
244 rh.ll = mul_u32_u32(u.l.high, mul) + rl.l.high; in mul_u64_u32_div()
/openbmc/u-boot/arch/arm/lib/
H A Dmuldi3.S29 mul xh, yl, xh
36 mul yh, xl, yh
37 mul xl, yl, xl
38 mul ip, yl, ip
/openbmc/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dclock.c43 unsigned i, div = 0, mul = 0, diff = 1 << 30; in at91_pll_calc() local
71 if (mul > 63) in at91_pll_calc()
85 mul = mul1; in at91_pll_calc()
92 return ret | ((mul - 1) << 16) | div; in at91_pll_calc()
100 unsigned mul, div; in at91_pll_rate() local
103 mul = (reg >> 16) & 0x7ff; in at91_pll_rate()
104 if (div && mul) { in at91_pll_rate()
106 freq *= mul + 1; in at91_pll_rate()
/openbmc/u-boot/drivers/clk/
H A Dclk_boston.c31 uint32_t in_rate, mul, div; in clk_boston_get_rate() local
40 mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL); in clk_boston_get_rate()
53 return (in_rate * mul * 1000000) / div; in clk_boston_get_rate()
H A Dclk_zynq.c133 u32 clk_ctrl, reset, pwrdwn, mul, bypass; in zynq_clk_get_pll_rate() local
144 mul = 1; in zynq_clk_get_pll_rate()
146 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; in zynq_clk_get_pll_rate()
148 return priv->ps_clk_freq * mul; in zynq_clk_get_pll_rate()
H A Dclk_pic32.c282 u32 v, idiv, mul; in pic32_get_mpll_rate() local
288 mul = (v >> MPLL_MULT_SHIFT) & MPLL_MULT; in pic32_get_mpll_rate()
292 rate = (SYS_POSC_CLK_HZ / idiv) * mul; in pic32_get_mpll_rate()
H A Dclk_zynqmp.c339 u32 clk_ctrl, reset, mul; in zynqmp_clk_get_pll_rate() local
358 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; in zynqmp_clk_get_pll_rate()
360 freq *= mul; in zynqmp_clk_get_pll_rate()
/openbmc/u-boot/arch/arm/mach-at91/armv7/
H A Dclock.c41 unsigned mul, div; in at91_pll_rate() local
44 mul = (reg >> 18) & 0x7f; in at91_pll_rate()
45 if (div && mul) { in at91_pll_rate()
47 freq *= mul + 1; in at91_pll_rate()
/openbmc/u-boot/arch/mips/lib/
H A Dcache_init.S64 mul \sz, \sz, \line_sz
77 mul \sz, \sz, $1
158 mul R_L2_SIZE, R_L2_LINE, t2
163 mul R_L2_SIZE, R_L2_SIZE, t2
201 mul R_L2_SIZE, R_L2_LINE, t1
207 mul R_L2_SIZE, R_L2_SIZE, t1
/openbmc/qemu/tests/tcg/tricore/asm/
H A Dtest_fmul.S5 TEST_D_DD_PSW(mul.f, 1, 0x974f4f0a, 0x84000b80, 0x1a0b1980, 0xbcbec42d)
/openbmc/qemu/util/
H A Dcutils.c231 int64_t mul; in do_strtosz() local
313 mul = suffix_mul(c, unit); in do_strtosz()
314 if (mul > 0) { in do_strtosz()
317 mul = suffix_mul(default_suffix, unit); in do_strtosz()
318 assert(mul > 0); in do_strtosz()
320 if (mul == 1) { in do_strtosz()
331 mulu64(&val, &valh, val, mul); in do_strtosz()
332 mulu64(&valf, &tmp, valf, mul); in do_strtosz()
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_mac16.S47 test_mulxx mul.aa, 0, a2, a3, 0xf7315a5a, 0xa5a5137f
51 test_mulxx mul.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f
55 test_mulxx mul.da, 2, m1, a3, 0xf7315a5a, 0xa5a5137f
59 test_mulxx mul.dd, 3, m0, m3, 0xf7315a5a, 0xa5a5137f
H A Dtest_dfp0_arith.S82 test_op2 mul.d, f0, f1, f2, F64_1 | 1, F64_1 | 1, \
86 test_op2 mul.d, f6, f7, f8, F64_MAX_2, F64_MAX_2, \
90 test_op2 mul.d, f6, f7, f8, F64_MIN_NORM, F64_MIN_NORM, \
94 test_op2 mul.d, f6, f7, f8, F64_PINF, F64_0, \
H A Dtest_fp0_arith.S126 test_op2 mul.s, f0, f1, f2, 0x3f800001, 0x3f800001, \
130 test_op2 mul.s, f6, f7, f8, 0x7f000000, 0x7f000000, \
134 test_op2 mul.s, f6, f7, f8, 0x00800001, 0x00800000, \
138 test_op2 mul.s, f6, f7, f8, 0x7f800000, 0x00000000, \
/openbmc/qemu/target/sh4/
H A Dop_helper.c164 int64_t mul = (int64_t)arg0 * arg1; in helper_macl() local
169 res = mac + mul; in helper_macl()
170 } else if (sadd64_overflow(mac, mul, &res)) { in helper_macl()
182 int32_t mul = arg0 * arg1; in helper_macw() local
192 if (sadd32_overflow(macl, mul, &res)) { in helper_macw()
200 env->mac += mul; in helper_macw()
/openbmc/u-boot/doc/device-tree-bindings/cpu/
H A Dnios2.txt25 - altr,has-mul: Specifies CPU hardware multipy support.
48 altr,has-mul = <1>;
/openbmc/u-boot/board/xilinx/microblaze-generic/
H A Dconfig.mk11 CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
/openbmc/openbmc/poky/meta/conf/machine/include/microblaze/
H A Dfeature-microblaze-math.inc16 …any('TUNE_FEATURES', ['multiply-low', 'multiply-high'], ' -mno-xl-soft-mul', ' -mxl-soft-mul', d)}"
/openbmc/u-boot/post/lib_powerpc/fpu/
H A DMakefile7 acc1.o compare-fp-1.o fpu.o mul-subnormal-single-1.o darwin-ldouble.o
/openbmc/qemu/hw/core/
H A Dtrace-events31 …t_mul_div(const char *clk, uint32_t oldmul, uint32_t mul, uint32_t olddiv, uint32_t div) "'%s', mu…
/openbmc/qemu/tests/tcg/mips/include/
H A Dwrappers_mips64r6.h74 DO_MIPS64R6__RD__RS_RT(MUL, mul)
/openbmc/qemu/tests/fp/
H A Dmeson.build16 'mul': 60,
107 'mul': 'ops',
/openbmc/qemu/hw/audio/
H A Dfmopl.h21 uint32_t mul; /* multiple :ML_TABLE[ML] */ member
/openbmc/u-boot/arch/x86/cpu/
H A Dsipi_vector.S112 mul %ecx

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