1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
262011840SMasahiro Yamada /*
362011840SMasahiro Yamada * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
462011840SMasahiro Yamada *
562011840SMasahiro Yamada * Copyright (C) 2005 David Brownell
662011840SMasahiro Yamada * Copyright (C) 2005 Ivan Kokshaysky
762011840SMasahiro Yamada * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
862011840SMasahiro Yamada */
962011840SMasahiro Yamada
1062011840SMasahiro Yamada #include <common.h>
1162011840SMasahiro Yamada #include <asm/io.h>
1262011840SMasahiro Yamada #include <asm/arch/hardware.h>
1362011840SMasahiro Yamada #include <asm/arch/at91_pmc.h>
1462011840SMasahiro Yamada #include <asm/arch/clk.h>
1562011840SMasahiro Yamada
1662011840SMasahiro Yamada #if !defined(CONFIG_AT91FAMILY)
1762011840SMasahiro Yamada # error You need to define CONFIG_AT91FAMILY in your board config!
1862011840SMasahiro Yamada #endif
1962011840SMasahiro Yamada
20be5e485cSWenyou Yang #define EN_PLLB_TIMEOUT 500
21be5e485cSWenyou Yang
2262011840SMasahiro Yamada DECLARE_GLOBAL_DATA_PTR;
2362011840SMasahiro Yamada
at91_css_to_rate(unsigned long css)2462011840SMasahiro Yamada static unsigned long at91_css_to_rate(unsigned long css)
2562011840SMasahiro Yamada {
2662011840SMasahiro Yamada switch (css) {
2762011840SMasahiro Yamada case AT91_PMC_MCKR_CSS_SLOW:
2862011840SMasahiro Yamada return CONFIG_SYS_AT91_SLOW_CLOCK;
2962011840SMasahiro Yamada case AT91_PMC_MCKR_CSS_MAIN:
3062011840SMasahiro Yamada return gd->arch.main_clk_rate_hz;
3162011840SMasahiro Yamada case AT91_PMC_MCKR_CSS_PLLA:
3262011840SMasahiro Yamada return gd->arch.plla_rate_hz;
3362011840SMasahiro Yamada case AT91_PMC_MCKR_CSS_PLLB:
3462011840SMasahiro Yamada return gd->arch.pllb_rate_hz;
3562011840SMasahiro Yamada }
3662011840SMasahiro Yamada
3762011840SMasahiro Yamada return 0;
3862011840SMasahiro Yamada }
3962011840SMasahiro Yamada
4062011840SMasahiro Yamada #ifdef CONFIG_USB_ATMEL
at91_pll_calc(unsigned main_freq,unsigned out_freq)4162011840SMasahiro Yamada static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
4262011840SMasahiro Yamada {
4362011840SMasahiro Yamada unsigned i, div = 0, mul = 0, diff = 1 << 30;
4462011840SMasahiro Yamada unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
4562011840SMasahiro Yamada
4662011840SMasahiro Yamada /* PLL output max 240 MHz (or 180 MHz per errata) */
4762011840SMasahiro Yamada if (out_freq > 240000000)
4862011840SMasahiro Yamada goto fail;
4962011840SMasahiro Yamada
5062011840SMasahiro Yamada for (i = 1; i < 256; i++) {
5162011840SMasahiro Yamada int diff1;
5262011840SMasahiro Yamada unsigned input, mul1;
5362011840SMasahiro Yamada
5462011840SMasahiro Yamada /*
5562011840SMasahiro Yamada * PLL input between 1MHz and 32MHz per spec, but lower
5662011840SMasahiro Yamada * frequences seem necessary in some cases so allow 100K.
5762011840SMasahiro Yamada * Warning: some newer products need 2MHz min.
5862011840SMasahiro Yamada */
5962011840SMasahiro Yamada input = main_freq / i;
6062011840SMasahiro Yamada #if defined(CONFIG_AT91SAM9G20)
6162011840SMasahiro Yamada if (input < 2000000)
6262011840SMasahiro Yamada continue;
6362011840SMasahiro Yamada #endif
6462011840SMasahiro Yamada if (input < 100000)
6562011840SMasahiro Yamada continue;
6662011840SMasahiro Yamada if (input > 32000000)
6762011840SMasahiro Yamada continue;
6862011840SMasahiro Yamada
6962011840SMasahiro Yamada mul1 = out_freq / input;
7062011840SMasahiro Yamada #if defined(CONFIG_AT91SAM9G20)
7162011840SMasahiro Yamada if (mul > 63)
7262011840SMasahiro Yamada continue;
7362011840SMasahiro Yamada #endif
7462011840SMasahiro Yamada if (mul1 > 2048)
7562011840SMasahiro Yamada continue;
7662011840SMasahiro Yamada if (mul1 < 2)
7762011840SMasahiro Yamada goto fail;
7862011840SMasahiro Yamada
7962011840SMasahiro Yamada diff1 = out_freq - input * mul1;
8062011840SMasahiro Yamada if (diff1 < 0)
8162011840SMasahiro Yamada diff1 = -diff1;
8262011840SMasahiro Yamada if (diff > diff1) {
8362011840SMasahiro Yamada diff = diff1;
8462011840SMasahiro Yamada div = i;
8562011840SMasahiro Yamada mul = mul1;
8662011840SMasahiro Yamada if (diff == 0)
8762011840SMasahiro Yamada break;
8862011840SMasahiro Yamada }
8962011840SMasahiro Yamada }
9062011840SMasahiro Yamada if (i == 256 && diff > (out_freq >> 5))
9162011840SMasahiro Yamada goto fail;
9262011840SMasahiro Yamada return ret | ((mul - 1) << 16) | div;
9362011840SMasahiro Yamada fail:
9462011840SMasahiro Yamada return 0;
9562011840SMasahiro Yamada }
9662011840SMasahiro Yamada #endif
9762011840SMasahiro Yamada
at91_pll_rate(u32 freq,u32 reg)9862011840SMasahiro Yamada static u32 at91_pll_rate(u32 freq, u32 reg)
9962011840SMasahiro Yamada {
10062011840SMasahiro Yamada unsigned mul, div;
10162011840SMasahiro Yamada
10262011840SMasahiro Yamada div = reg & 0xff;
10362011840SMasahiro Yamada mul = (reg >> 16) & 0x7ff;
10462011840SMasahiro Yamada if (div && mul) {
10562011840SMasahiro Yamada freq /= div;
10662011840SMasahiro Yamada freq *= mul + 1;
10762011840SMasahiro Yamada } else
10862011840SMasahiro Yamada freq = 0;
10962011840SMasahiro Yamada
11062011840SMasahiro Yamada return freq;
11162011840SMasahiro Yamada }
11262011840SMasahiro Yamada
at91_clock_init(unsigned long main_clock)11362011840SMasahiro Yamada int at91_clock_init(unsigned long main_clock)
11462011840SMasahiro Yamada {
11562011840SMasahiro Yamada unsigned freq, mckr;
11662011840SMasahiro Yamada at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
11762011840SMasahiro Yamada #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
11862011840SMasahiro Yamada unsigned tmp;
11962011840SMasahiro Yamada /*
12062011840SMasahiro Yamada * When the bootloader initialized the main oscillator correctly,
12162011840SMasahiro Yamada * there's no problem using the cycle counter. But if it didn't,
12262011840SMasahiro Yamada * or when using oscillator bypass mode, we must be told the speed
12362011840SMasahiro Yamada * of the main clock.
12462011840SMasahiro Yamada */
12562011840SMasahiro Yamada if (!main_clock) {
12662011840SMasahiro Yamada do {
12762011840SMasahiro Yamada tmp = readl(&pmc->mcfr);
12862011840SMasahiro Yamada } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
12962011840SMasahiro Yamada tmp &= AT91_PMC_MCFR_MAINF_MASK;
13062011840SMasahiro Yamada main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
13162011840SMasahiro Yamada }
13262011840SMasahiro Yamada #endif
13362011840SMasahiro Yamada gd->arch.main_clk_rate_hz = main_clock;
13462011840SMasahiro Yamada
13562011840SMasahiro Yamada /* report if PLLA is more than mildly overclocked */
13662011840SMasahiro Yamada gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
13762011840SMasahiro Yamada
13862011840SMasahiro Yamada #ifdef CONFIG_USB_ATMEL
13962011840SMasahiro Yamada /*
14062011840SMasahiro Yamada * USB clock init: choose 48 MHz PLLB value,
14162011840SMasahiro Yamada * disable 48MHz clock during usb peripheral suspend.
14262011840SMasahiro Yamada *
14362011840SMasahiro Yamada * REVISIT: assumes MCK doesn't derive from PLLB!
14462011840SMasahiro Yamada */
14562011840SMasahiro Yamada gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
14662011840SMasahiro Yamada AT91_PMC_PLLBR_USBDIV_2;
14762011840SMasahiro Yamada gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
14862011840SMasahiro Yamada gd->arch.at91_pllb_usb_init);
14962011840SMasahiro Yamada #endif
15062011840SMasahiro Yamada
15162011840SMasahiro Yamada /*
15262011840SMasahiro Yamada * MCK and CPU derive from one of those primary clocks.
15362011840SMasahiro Yamada * For now, assume this parentage won't change.
15462011840SMasahiro Yamada */
15562011840SMasahiro Yamada mckr = readl(&pmc->mckr);
15662011840SMasahiro Yamada #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
15762011840SMasahiro Yamada || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
15862011840SMasahiro Yamada /* plla divisor by 2 */
15962011840SMasahiro Yamada gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
16062011840SMasahiro Yamada #endif
16162011840SMasahiro Yamada gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
16262011840SMasahiro Yamada freq = gd->arch.mck_rate_hz;
16362011840SMasahiro Yamada
164806a5a39SHeiko Schocher #if defined(CONFIG_AT91SAM9X5)
165806a5a39SHeiko Schocher /* different in prescale on at91sam9x5 */
166806a5a39SHeiko Schocher freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4));
167806a5a39SHeiko Schocher #else
16862011840SMasahiro Yamada freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
169806a5a39SHeiko Schocher #endif
170806a5a39SHeiko Schocher
17162011840SMasahiro Yamada #if defined(CONFIG_AT91SAM9G20)
17262011840SMasahiro Yamada /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
17362011840SMasahiro Yamada gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
17462011840SMasahiro Yamada freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
17562011840SMasahiro Yamada if (mckr & AT91_PMC_MCKR_MDIV_MASK)
17662011840SMasahiro Yamada freq /= 2; /* processor clock division */
17762011840SMasahiro Yamada #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
17862011840SMasahiro Yamada || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
17962011840SMasahiro Yamada /* mdiv <==> divisor
18062011840SMasahiro Yamada * 0 <==> 1
18162011840SMasahiro Yamada * 1 <==> 2
18262011840SMasahiro Yamada * 2 <==> 4
18362011840SMasahiro Yamada * 3 <==> 3
18462011840SMasahiro Yamada */
18562011840SMasahiro Yamada gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
18662011840SMasahiro Yamada (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
18762011840SMasahiro Yamada ? freq / 3
18862011840SMasahiro Yamada : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
18962011840SMasahiro Yamada #else
19062011840SMasahiro Yamada gd->arch.mck_rate_hz = freq /
19162011840SMasahiro Yamada (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
19262011840SMasahiro Yamada #endif
19362011840SMasahiro Yamada gd->arch.cpu_clk_rate_hz = freq;
19462011840SMasahiro Yamada
19562011840SMasahiro Yamada return 0;
19662011840SMasahiro Yamada }
19762011840SMasahiro Yamada
19862011840SMasahiro Yamada #if !defined(AT91_PLL_LOCK_TIMEOUT)
19962011840SMasahiro Yamada #define AT91_PLL_LOCK_TIMEOUT 1000000
20062011840SMasahiro Yamada #endif
20162011840SMasahiro Yamada
at91_plla_init(u32 pllar)20262011840SMasahiro Yamada void at91_plla_init(u32 pllar)
20362011840SMasahiro Yamada {
20462011840SMasahiro Yamada struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
20562011840SMasahiro Yamada
20662011840SMasahiro Yamada writel(pllar, &pmc->pllar);
20772cb3b6bSBo Shen while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
20872cb3b6bSBo Shen ;
20962011840SMasahiro Yamada }
at91_pllb_init(u32 pllbr)21062011840SMasahiro Yamada void at91_pllb_init(u32 pllbr)
21162011840SMasahiro Yamada {
21262011840SMasahiro Yamada struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
21362011840SMasahiro Yamada
21462011840SMasahiro Yamada writel(pllbr, &pmc->pllbr);
21572cb3b6bSBo Shen while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
21672cb3b6bSBo Shen ;
21762011840SMasahiro Yamada }
21862011840SMasahiro Yamada
at91_mck_init(u32 mckr)21962011840SMasahiro Yamada void at91_mck_init(u32 mckr)
22062011840SMasahiro Yamada {
22162011840SMasahiro Yamada struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
22262011840SMasahiro Yamada u32 tmp;
22362011840SMasahiro Yamada
22462011840SMasahiro Yamada tmp = readl(&pmc->mckr);
22572cb3b6bSBo Shen tmp &= ~AT91_PMC_MCKR_PRES_MASK;
22672cb3b6bSBo Shen tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
22762011840SMasahiro Yamada writel(tmp, &pmc->mckr);
22872cb3b6bSBo Shen while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
22972cb3b6bSBo Shen ;
23062011840SMasahiro Yamada
23172cb3b6bSBo Shen tmp = readl(&pmc->mckr);
23272cb3b6bSBo Shen tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
23372cb3b6bSBo Shen tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
23472cb3b6bSBo Shen writel(tmp, &pmc->mckr);
23572cb3b6bSBo Shen while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
23672cb3b6bSBo Shen ;
23772cb3b6bSBo Shen
23872cb3b6bSBo Shen tmp = readl(&pmc->mckr);
23972cb3b6bSBo Shen tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
24072cb3b6bSBo Shen tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
24172cb3b6bSBo Shen writel(tmp, &pmc->mckr);
24272cb3b6bSBo Shen while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
24372cb3b6bSBo Shen ;
24472cb3b6bSBo Shen
24572cb3b6bSBo Shen tmp = readl(&pmc->mckr);
24672cb3b6bSBo Shen tmp &= ~AT91_PMC_MCKR_CSS_MASK;
24772cb3b6bSBo Shen tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
24872cb3b6bSBo Shen writel(tmp, &pmc->mckr);
24972cb3b6bSBo Shen while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
25072cb3b6bSBo Shen ;
25162011840SMasahiro Yamada }
252be5e485cSWenyou Yang
at91_pllb_clk_enable(u32 pllbr)253be5e485cSWenyou Yang int at91_pllb_clk_enable(u32 pllbr)
254be5e485cSWenyou Yang {
255be5e485cSWenyou Yang struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
256be5e485cSWenyou Yang ulong start_time, tmp_time;
257be5e485cSWenyou Yang
258be5e485cSWenyou Yang start_time = get_timer(0);
259be5e485cSWenyou Yang writel(pllbr, &pmc->pllbr);
260be5e485cSWenyou Yang while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
261be5e485cSWenyou Yang tmp_time = get_timer(0);
262be5e485cSWenyou Yang if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
263be5e485cSWenyou Yang printf("ERROR: failed to enable PLLB\n");
264be5e485cSWenyou Yang return -1;
265be5e485cSWenyou Yang }
266be5e485cSWenyou Yang }
267be5e485cSWenyou Yang
268be5e485cSWenyou Yang return 0;
269be5e485cSWenyou Yang }
270be5e485cSWenyou Yang
at91_pllb_clk_disable(void)271be5e485cSWenyou Yang int at91_pllb_clk_disable(void)
272be5e485cSWenyou Yang {
273be5e485cSWenyou Yang struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
274be5e485cSWenyou Yang ulong start_time, tmp_time;
275be5e485cSWenyou Yang
276be5e485cSWenyou Yang start_time = get_timer(0);
277be5e485cSWenyou Yang writel(0, &pmc->pllbr);
278be5e485cSWenyou Yang while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
279be5e485cSWenyou Yang tmp_time = get_timer(0);
280be5e485cSWenyou Yang if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
281be5e485cSWenyou Yang printf("ERROR: failed to disable PLLB\n");
282be5e485cSWenyou Yang return -1;
283be5e485cSWenyou Yang }
284be5e485cSWenyou Yang }
285be5e485cSWenyou Yang
286be5e485cSWenyou Yang return 0;
287be5e485cSWenyou Yang }
288