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/openbmc/linux/tools/testing/selftests/kvm/x86_64/
H A Dhyperv_features.c47 GUEST_ASSERT(msr->idx); in guest_msr()
49 if (msr->write) in guest_msr()
50 vector = wrmsr_safe(msr->idx, msr->write_val); in guest_msr()
52 if (!vector && (!msr->write || !is_write_only_msr(msr->idx))) in guest_msr()
58 msr->idx, msr->write ? "WR" : "RD", vector); in guest_msr()
62 msr->idx, msr->write ? "WR" : "RD", vector); in guest_msr()
67 if (msr->write) in guest_msr()
70 msr->idx, msr->write_val, msr_val); in guest_msr()
187 msr->write = true; in guest_test_msrs_access()
216 msr->write = true; in guest_test_msrs_access()
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H A Duserspace_msr_exit_test.c416 run->msr.index, msr_index); in process_rdmsr()
418 switch (run->msr.index) { in process_rdmsr()
420 run->msr.data = 0; in process_rdmsr()
423 run->msr.error = 1; in process_rdmsr()
429 run->msr.data = MSR_FS_BASE; in process_rdmsr()
450 switch (run->msr.index) { in process_wrmsr()
452 if (run->msr.data != 0) in process_wrmsr()
453 run->msr.error = 1; in process_wrmsr()
456 if (run->msr.data != 1) in process_wrmsr()
457 run->msr.error = 1; in process_wrmsr()
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H A Dkvm_pv_test.c20 #define TEST_MSR(msr) { .idx = msr, .name = #msr } argument
22 #define PR_MSR(msr) ucall(UCALL_PR_MSR, 1, msr) argument
41 static void test_msr(struct msr_data *msr) in test_msr() argument
46 PR_MSR(msr); in test_msr()
48 vector = rdmsr_safe(msr->idx, &ignored); in test_msr()
51 vector = wrmsr_safe(msr->idx, 0); in test_msr()
100 struct msr_data *msr = (struct msr_data *)uc->args[0]; in pr_msr() local
102 pr_info("testing msr: %s (%#x)\n", msr->name, msr->idx); in pr_msr()
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dmodel_206ax.c34 msr_t msr; in enable_vmx() local
54 msr.hi = 0; in enable_vmx()
55 msr.lo = 0; in enable_vmx()
226 msr_t msr; in configure_c_states() local
288 msr_t msr; in configure_thermal_target() local
307 msr_t msr; in configure_misc() local
328 msr_t msr; in enable_lapic_tpr() local
338 msr_t msr; in configure_dca_cap() local
373 msr_t msr; in set_energy_perf_bias() local
386 msr_t msr; in configure_mca() local
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/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dcpu.c232 msr_t msr; in initialize_vr_config() local
437 msr_t msr; in broadwell_init() local
459 msr_t msr; in configure_mca() local
479 msr_t msr; in enable_lapic_tpr() local
489 msr_t msr; in configure_c_states() local
546 msr_t msr; in configure_misc() local
568 msr_t msr; in configure_thermal_target() local
586 msr_t msr; in configure_dca_cap() local
599 msr_t msr; in set_energy_perf_bias() local
650 msr_t msr; in cpu_set_power_limits() local
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/openbmc/linux/arch/x86/kernel/cpu/
H A Dperfctr-watchdog.c51 if (msr >= MSR_F15H_PERF_CTR) in nmi_perfctr_msr_to_bit()
53 return msr - MSR_K7_PERFCTR0; in nmi_perfctr_msr_to_bit()
60 return msr - MSR_P6_PERFCTR0; in nmi_perfctr_msr_to_bit()
62 return msr - MSR_KNC_PERFCTR0; in nmi_perfctr_msr_to_bit()
64 return msr - MSR_P4_BPU_PERFCTR0; in nmi_perfctr_msr_to_bit()
84 if (msr >= MSR_F15H_PERF_CTL) in nmi_evntsel_msr_to_bit()
86 return msr - MSR_K7_EVNTSEL0; in nmi_evntsel_msr_to_bit()
93 return msr - MSR_P6_EVNTSEL0; in nmi_evntsel_msr_to_bit()
95 return msr - MSR_KNC_EVNTSEL0; in nmi_evntsel_msr_to_bit()
97 return msr - MSR_P4_BSU_ESCR0; in nmi_evntsel_msr_to_bit()
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/openbmc/u-boot/arch/x86/include/asm/
H A Dmsr.h26 struct msr { struct
38 struct msr reg; argument
39 struct msr *msrs;
137 wrmsrl(msr, val); in msr_clrsetbits_64()
146 wrmsrl(msr, val); in msr_setbits_64()
155 wrmsrl(msr, val); in msr_clrbits_64()
173 gprs[1] = msr; in rdmsrl_amd_safe()
188 gprs[1] = msr; in wrmsrl_amd_safe()
214 rdmsr(msr_num, msr.lo, msr.hi); in msr_read()
216 return msr; in msr_read()
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/openbmc/linux/arch/x86/include/asm/
H A Dmsr.h17 struct msr reg;
18 struct msr *msrs;
102 u64 __val = __rdmsr((msr)); \
108 __wrmsr(msr, low, high)
118 val = __rdmsr(msr); in native_read_msr()
135 : "c" (msr)); in native_read_msr_safe()
145 __wrmsr(msr, low, high); in native_write_msr()
257 #define rdmsrl(msr, val) \ argument
308 struct msr *msrs_alloc(void);
348 struct msr *msrs) in rdmsr_on_cpus()
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H A Dmsr-trace.h3 #define TRACE_SYSTEM msr
6 #define TRACE_INCLUDE_FILE msr-trace
22 TP_PROTO(unsigned msr, u64 val, int failed),
23 TP_ARGS(msr, val, failed),
25 __field( unsigned, msr )
30 __entry->msr = msr;
35 __entry->msr,
41 TP_PROTO(unsigned msr, u64 val, int failed),
42 TP_ARGS(msr, val, failed)
47 TP_ARGS(msr, val, failed)
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/openbmc/linux/arch/x86/lib/
H A Dmsr.c9 struct msr *msrs_alloc(void) in msrs_alloc()
11 struct msr *msrs = NULL; in msrs_alloc()
13 msrs = alloc_percpu(struct msr); in msrs_alloc()
23 void msrs_free(struct msr *msrs) in msrs_free()
39 static int msr_read(u32 msr, struct msr *m) in msr_read() argument
44 err = rdmsrl_safe(msr, &val); in msr_read()
59 static int msr_write(u32 msr, struct msr *m) in msr_write() argument
61 return wrmsrl_safe(msr, m->q); in msr_write()
66 struct msr m, m1; in __flip_bit()
72 err = msr_read(msr, &m); in __flip_bit()
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/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_hv_tm.c19 u64 msr = vcpu->arch.shregs.msr; in emulate_tx_failure() local
25 if (msr & MSR_PR) { in emulate_tx_failure()
45 u64 msr = vcpu->arch.shregs.msr; in kvmhv_p9_tm_emulation() local
111 msr = (msr & ~MSR_TS_MASK) | MSR_TS_T; in kvmhv_p9_tm_emulation()
112 vcpu->arch.shregs.msr = msr; in kvmhv_p9_tm_emulation()
147 if (!(msr & MSR_TM)) { in kvmhv_p9_tm_emulation()
161 msr = (msr & ~MSR_TS_MASK) | MSR_TS_T; in kvmhv_p9_tm_emulation()
164 msr = (msr & ~MSR_TS_MASK) | MSR_TS_S; in kvmhv_p9_tm_emulation()
166 vcpu->arch.shregs.msr = msr; in kvmhv_p9_tm_emulation()
179 if (!(msr & MSR_TM)) { in kvmhv_p9_tm_emulation()
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H A Dbook3s_hv_tm_builtin.c23 u64 newmsr, msr, bescr; in kvmhv_p9_tm_emulation_early() local
45 vcpu->arch.shregs.msr = newmsr; in kvmhv_p9_tm_emulation_early()
52 msr = vcpu->arch.shregs.msr; in kvmhv_p9_tm_emulation_early()
57 ((msr & MSR_PR) && !(mfspr(SPRN_FSCR) & FSCR_EBB))) in kvmhv_p9_tm_emulation_early()
67 msr = (msr & ~MSR_TS_MASK) | MSR_TS_T; in kvmhv_p9_tm_emulation_early()
68 vcpu->arch.shregs.msr = msr; in kvmhv_p9_tm_emulation_early()
77 msr = vcpu->arch.shregs.msr; in kvmhv_p9_tm_emulation_early()
82 newmsr = (newmsr & ~MSR_LE) | (msr & MSR_LE); in kvmhv_p9_tm_emulation_early()
84 vcpu->arch.shregs.msr = newmsr; in kvmhv_p9_tm_emulation_early()
90 msr = vcpu->arch.shregs.msr; in kvmhv_p9_tm_emulation_early()
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/openbmc/linux/drivers/powercap/
H A Dintel_rapl_msr.c37 .reg_unit.msr = MSR_RAPL_POWER_UNIT,
42 .regs[RAPL_DOMAIN_PP0][RAPL_DOMAIN_REG_LIMIT].msr = MSR_PP0_POWER_LIMIT,
44 .regs[RAPL_DOMAIN_PP0][RAPL_DOMAIN_REG_POLICY].msr = MSR_PP0_POLICY,
45 .regs[RAPL_DOMAIN_PP1][RAPL_DOMAIN_REG_LIMIT].msr = MSR_PP1_POWER_LIMIT,
47 .regs[RAPL_DOMAIN_PP1][RAPL_DOMAIN_REG_POLICY].msr = MSR_PP1_POLICY,
60 .reg_unit.msr = MSR_AMD_RAPL_POWER_UNIT,
106 if (rdmsrl_safe_on_cpu(cpu, ra->reg.msr, &ra->value)) { in rapl_msr_read_raw()
107 pr_debug("failed to read msr 0x%x on cpu %d\n", ra->reg.msr, cpu); in rapl_msr_read_raw()
119 ra->err = rdmsrl_safe(ra->reg.msr, &val); in rapl_msr_update_func()
126 ra->err = wrmsrl_safe(ra->reg.msr, val); in rapl_msr_update_func()
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/openbmc/linux/arch/m68k/bvme6000/
H A Dconfig.c169 unsigned char msr; in bvme6000_timer_int() local
172 msr = rtc->msr & 0xc0; in bvme6000_timer_int()
173 rtc->msr = msr | 0x20; /* Ack the interrupt */ in bvme6000_timer_int()
194 unsigned char msr = rtc->msr & 0xc0; in bvme6000_sched_init() local
214 rtc->msr = msr; in bvme6000_sched_init()
236 unsigned char msr, msb; in bvme6000_read_clk() local
242 msr = rtc->msr & 0xc0; in bvme6000_read_clk()
247 t1int = rtc->msr & 0x20; in bvme6000_read_clk()
262 rtc->msr = msr; in bvme6000_read_clk()
289 unsigned char msr = rtc->msr & 0xc0; in bvme6000_hwclk() local
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/openbmc/u-boot/arch/arm/include/asm/
H A Dmacro.h160 msr cntvoff_el2, xzr
172 msr sctlr_el2, \tmp
200 msr scr_el3, \tmp
206 msr spsr_el3, \tmp
207 msr elr_el3, \ep
218 msr scr_el3, \tmp
225 msr spsr_el3, \tmp
252 msr vpidr_el2, \tmp
292 msr hcr_el2, \tmp
298 msr spsr_el2, \tmp
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/openbmc/linux/arch/x86/kvm/
H A Dmtrr.c31 return !(msr & 0x1); in is_mtrr_base_msr()
35 unsigned int msr) in var_mtrr_msr_to_range() argument
44 switch (msr) { in msr_mtrr_valid()
73 if (!msr_mtrr_valid(msr)) in kvm_mtrr_valid()
76 if (msr == MSR_MTRRdefType) { in kvm_mtrr_valid()
80 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { in kvm_mtrr_valid()
92 if ((msr & 1) == 0) { in kvm_mtrr_valid()
196 switch (msr) { in fixed_msr_to_seg_unit()
393 update_mtrr(vcpu, msr); in kvm_mtrr_set_msr()
402 if (msr == MSR_MTRRcap) { in kvm_mtrr_get_msr()
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/openbmc/qemu/target/ppc/
H A Dexcp_helper.c295 bool mmu_all_on = ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1); in ppc_excp_apply_ail()
403 assert((msr & env->msr_mask) == msr); in powerpc_set_excp_state()
413 env->msr = msr; in powerpc_set_excp_state()
489 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_40x()
596 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_6xx()
739 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_7xx()
889 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_74xx()
1037 msr = env->msr; in powerpc_excp_booke()
1334 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_books()
2500 msr |= env->msr & (1ULL << MSR_SF); in ppc_cpu_do_fwnmi_machine_check()
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/openbmc/linux/tools/power/x86/turbostat/
H A Dturbostat.c2445 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); in dump_nhm_platform_info()
4062 msr = (msr >> 30) & 1; in check_tcc_offset()
4423 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis"); in print_hwp()
4430 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x4) ? "" : "No-"); in print_hwp()
4970 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); in print_rapl()
5003 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); in print_rapl()
5017 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); in print_rapl()
5029 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); in print_rapl()
5337 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : ""); in decode_feature_control_msr()
5367 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "", in decode_misc_feature_control()
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/openbmc/linux/arch/x86/xen/
H A Dpmu.c138 if ((msr >= MSR_F15H_PERF_CTL && in is_amd_pmu_msr()
140 (msr >= MSR_K7_EVNTSEL0 && in is_amd_pmu_msr()
214 switch (msr) { in xen_intel_pmu_emulate()
274 ((msr >= MSR_K7_EVNTSEL0) && (msr <= MSR_K7_PERFCTR3))) in xen_amd_pmu_emulate()
275 msr = get_fam15h_addr(msr); in xen_amd_pmu_emulate()
279 if (msr == amd_ctrls_base + off) { in xen_amd_pmu_emulate()
307 if (is_amd_pmu_msr(msr)) in pmu_msr_chk_emulated()
326 : native_read_msr(msr); in pmu_msr_read()
344 native_write_msr(msr, low, high); in pmu_msr_write()
358 uint32_t msr; in xen_amd_read_pmc() local
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/openbmc/linux/arch/x86/events/
H A Dprobe.c19 perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data) in perf_msr_probe() argument
29 if (!msr[bit].no_check) { in perf_msr_probe()
30 struct attribute_group *grp = msr[bit].grp; in perf_msr_probe()
40 if (!msr[bit].msr) in perf_msr_probe()
43 if (msr[bit].test && !msr[bit].test(bit, data)) in perf_msr_probe()
46 if (rdmsrl_safe(msr[bit].msr, &val)) in perf_msr_probe()
49 mask = msr[bit].mask; in perf_msr_probe()
/openbmc/linux/arch/microblaze/kernel/
H A Dprocess.c72 local_save_flags(childregs->msr); in copy_thread()
73 ti->cpu_context.msr = childregs->msr & ~MSR_IE; in copy_thread()
83 childregs->msr |= MSR_UMS; in copy_thread()
95 childregs->msr &= ~MSR_EIP; in copy_thread()
96 childregs->msr |= MSR_IE; in copy_thread()
97 childregs->msr &= ~MSR_VM; in copy_thread()
98 childregs->msr |= MSR_VMS; in copy_thread()
101 ti->cpu_context.msr = (childregs->msr|MSR_VM); in copy_thread()
103 ti->cpu_context.msr &= ~MSR_IE; in copy_thread()
128 regs->msr |= MSR_UMS; in start_thread()
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/openbmc/linux/arch/x86/kvm/svm/
H A Dpmu.c47 switch (msr) { in get_gp_pmc_amd()
56 if (!(msr & 0x1) != (type == PMU_TYPE_EVNTSEL)) in get_gp_pmc_amd()
62 idx = msr - MSR_K7_EVNTSEL0; in get_gp_pmc_amd()
67 idx = msr - MSR_K7_PERFCTR0; in get_gp_pmc_amd()
102 pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER); in amd_msr_idx_to_pmc()
112 switch (msr) { in amd_is_valid_msr()
122 if (msr > MSR_F15H_PERF_CTR5 && in amd_is_valid_msr()
128 return amd_msr_idx_to_pmc(vcpu, msr); in amd_is_valid_msr()
135 u32 msr = msr_info->index; in amd_pmu_get_msr() local
138 pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER); in amd_pmu_get_msr()
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/openbmc/linux/arch/powerpc/kernel/
H A Dsignal_64.c130 unsigned long msr = regs->msr; in __unsafe_setup_sigcontext() local
147 msr |= MSR_VEC; in __unsafe_setup_sigcontext()
163 msr &= ~MSR_VSX; in __unsafe_setup_sigcontext()
176 msr |= MSR_VSX; in __unsafe_setup_sigcontext()
237 msr |= tsk->thread.ckpt_regs.msr & (MSR_FP | MSR_VEC | MSR_VSX); in setup_tm_sigcontexts()
263 msr |= MSR_VEC; in setup_tm_sigcontexts()
285 if (msr & MSR_FP) in setup_tm_sigcontexts()
310 msr |= MSR_VSX; in setup_tm_sigcontexts()
576 regs_set_return_msr(regs, regs->msr | (msr & MSR_TS_MASK)); in restore_tm_sigcontexts()
865 unsigned long msr = regs->msr; in handle_rt_signal64() local
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/openbmc/linux/arch/arm64/kvm/hyp/nvhe/
H A Dhyp-init.S91 msr mair_el2, x1
94 msr hcr_el2, x1
103 msr tpidr_el2, x0
110 msr tpidr_el2, x1
113 msr vttbr_el2, x1
116 msr vtcr_el2, x1
123 msr ttbr0_el2, x2
130 msr tcr_el2, x0
157 msr vbar_el2, x0
230 msr elr_el2, x1
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/openbmc/u-boot/arch/x86/cpu/
H A Dlapic.c68 msr_t msr; in enable_lapic() local
70 msr = msr_read(MSR_IA32_APICBASE); in enable_lapic()
71 msr.hi &= 0xffffff00; in enable_lapic()
72 msr.lo |= MSR_IA32_APICBASE_ENABLE; in enable_lapic()
73 msr.lo &= ~MSR_IA32_APICBASE_BASE; in enable_lapic()
74 msr.lo |= LAPIC_DEFAULT_BASE; in enable_lapic()
75 msr_write(MSR_IA32_APICBASE, msr); in enable_lapic()
82 msr_t msr; in disable_lapic() local
84 msr = msr_read(MSR_IA32_APICBASE); in disable_lapic()
85 msr.lo &= ~MSR_IA32_APICBASE_ENABLE; in disable_lapic()
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