Lines Matching refs:msr
104 msr_t msr, perf_ctl, platform_info; in set_max_freq() local
111 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); in set_max_freq()
112 perf_ctl.lo = (msr.lo & 0xff) << 8; in set_max_freq()
115 msr = msr_read(MSR_PLATFORM_INFO); in set_max_freq()
116 perf_ctl.lo = msr.lo & 0xff00; in set_max_freq()
232 msr_t msr; in initialize_vr_config() local
237 msr = msr_read(MSR_VR_CURRENT_CONFIG); in initialize_vr_config()
242 msr.hi &= 0xc0000000; in initialize_vr_config()
243 msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */ in initialize_vr_config()
244 msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */ in initialize_vr_config()
245 msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */ in initialize_vr_config()
246 msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ in initialize_vr_config()
248 msr_write(MSR_VR_CURRENT_CONFIG, msr); in initialize_vr_config()
251 msr = msr_read(MSR_VR_MISC_CONFIG); in initialize_vr_config()
253 msr.hi &= ~(0x3ff << (40 - 32)); in initialize_vr_config()
254 msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ in initialize_vr_config()
256 msr.hi &= ~0xff; in initialize_vr_config()
258 msr.hi &= ~(1 << (51 - 32)); in initialize_vr_config()
260 msr.hi |= (1 << (52 - 32)); in initialize_vr_config()
262 msr.hi &= ~(0x3 << (53 - 32)); in initialize_vr_config()
268 msr.hi |= ((ramp & 0x3) << (53 - 32)); in initialize_vr_config()
270 msr.hi &= ~(1 << (50 - 32)); in initialize_vr_config()
273 msr.hi |= (0x01 << (53 - 32)); in initialize_vr_config()
275 msr.hi |= (1 << (50 - 32)); in initialize_vr_config()
278 msr.lo &= ~0xff000000; in initialize_vr_config()
281 msr.lo |= (min_vid & 0xff) << 24; in initialize_vr_config()
282 msr_write(MSR_VR_MISC_CONFIG, msr); in initialize_vr_config()
285 msr = msr_read(MSR_VR_MISC_CONFIG2); in initialize_vr_config()
286 msr.lo &= ~0xffff; in initialize_vr_config()
292 msr.lo |= 0x006a; /* 1.56V */ in initialize_vr_config()
294 msr.lo |= 0x006f; /* 1.60V */ in initialize_vr_config()
295 msr_write(MSR_VR_MISC_CONFIG2, msr); in initialize_vr_config()
409 msr_t msr, perf_ctl; in set_max_ratio() local
415 msr = msr_read(MSR_NHM_TURBO_RATIO_LIMIT); in set_max_ratio()
416 perf_ctl.lo = (msr.lo & 0xff) << 8; in set_max_ratio()
419 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); in set_max_ratio()
420 perf_ctl.lo = (msr.lo & 0xff) << 8; in set_max_ratio()
423 msr = msr_read(MSR_PLATFORM_INFO); in set_max_ratio()
424 perf_ctl.lo = msr.lo & 0xff00; in set_max_ratio()
437 msr_t msr; in broadwell_init() local
440 msr = msr_read(CORE_THREAD_COUNT_MSR); in broadwell_init()
441 num_threads = (msr.lo >> 0) & 0xffff; in broadwell_init()
442 num_cores = (msr.lo >> 16) & 0xffff; in broadwell_init()
459 msr_t msr; in configure_mca() local
464 msr = msr_read(mcg_cap_msr); in configure_mca()
465 num_banks = msr.lo & 0xff; in configure_mca()
466 msr.lo = 0; in configure_mca()
467 msr.hi = 0; in configure_mca()
474 msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr); in configure_mca()
479 msr_t msr; in enable_lapic_tpr() local
481 msr = msr_read(MSR_PIC_MSG_CONTROL); in enable_lapic_tpr()
482 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ in enable_lapic_tpr()
483 msr_write(MSR_PIC_MSG_CONTROL, msr); in enable_lapic_tpr()
489 msr_t msr; in configure_c_states() local
491 msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL); in configure_c_states()
492 msr.lo |= (1 << 31); /* Timed MWAIT Enable */ in configure_c_states()
493 msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */ in configure_c_states()
494 msr.lo |= (1 << 29); /* Package c-state Demotion Enable */ in configure_c_states()
495 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */ in configure_c_states()
496 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */ in configure_c_states()
497 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */ in configure_c_states()
498 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */ in configure_c_states()
499 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */ in configure_c_states()
501 msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr); in configure_c_states()
503 msr = msr_read(MSR_MISC_PWR_MGMT); in configure_c_states()
504 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */ in configure_c_states()
505 msr_write(MSR_MISC_PWR_MGMT, msr); in configure_c_states()
507 msr = msr_read(MSR_POWER_CTL); in configure_c_states()
508 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */ in configure_c_states()
509 msr.lo |= (1 << 1); /* C1E Enable */ in configure_c_states()
510 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */ in configure_c_states()
511 msr_write(MSR_POWER_CTL, msr); in configure_c_states()
514 msr.hi = 0; in configure_c_states()
515 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; in configure_c_states()
516 msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr); in configure_c_states()
519 msr.hi = 0; in configure_c_states()
520 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; in configure_c_states()
521 msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr); in configure_c_states()
524 msr.hi = 0; in configure_c_states()
525 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; in configure_c_states()
526 msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr); in configure_c_states()
529 msr.hi = 0; in configure_c_states()
530 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; in configure_c_states()
531 msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr); in configure_c_states()
534 msr.hi = 0; in configure_c_states()
535 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; in configure_c_states()
536 msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr); in configure_c_states()
539 msr.hi = 0; in configure_c_states()
540 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; in configure_c_states()
541 msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr); in configure_c_states()
546 msr_t msr; in configure_misc() local
548 msr = msr_read(MSR_IA32_MISC_ENABLE); in configure_misc()
549 msr.lo |= (1 << 0); /* Fast String enable */ in configure_misc()
550 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ in configure_misc()
551 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ in configure_misc()
552 msr_write(MSR_IA32_MISC_ENABLE, msr); in configure_misc()
555 msr.lo = 0; in configure_misc()
556 msr.hi = 0; in configure_misc()
557 msr_write(MSR_IA32_THERM_INTERRUPT, msr); in configure_misc()
560 msr.lo = 1 << 4; in configure_misc()
561 msr.hi = 0; in configure_misc()
562 msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr); in configure_misc()
568 msr_t msr; in configure_thermal_target() local
574 msr = msr_read(MSR_PLATFORM_INFO); in configure_thermal_target()
575 if ((msr.lo & (1 << 30)) && tcc_offset) { in configure_thermal_target()
576 msr = msr_read(MSR_TEMPERATURE_TARGET); in configure_thermal_target()
577 msr.lo &= ~(0xf << 24); /* Bits 27:24 */ in configure_thermal_target()
578 msr.lo |= (tcc_offset & 0xf) << 24; in configure_thermal_target()
579 msr_write(MSR_TEMPERATURE_TARGET, msr); in configure_thermal_target()
586 msr_t msr; in configure_dca_cap() local
591 msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP); in configure_dca_cap()
592 msr.lo |= 1; in configure_dca_cap()
593 msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr); in configure_dca_cap()
599 msr_t msr; in set_energy_perf_bias() local
608 msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS); in set_energy_perf_bias()
609 msr.lo &= ~0xf; in set_energy_perf_bias()
610 msr.lo |= policy & 0xf; in set_energy_perf_bias()
611 msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr); in set_energy_perf_bias()
650 msr_t msr; in cpu_set_power_limits() local
656 msr = msr_read(MSR_PLATFORM_INFO); in cpu_set_power_limits()
660 if (!(msr.lo & PLATFORM_INFO_SET_TDP)) in cpu_set_power_limits()
664 msr = msr_read(MSR_PKG_POWER_SKU_UNIT); in cpu_set_power_limits()
665 power_unit = 2 << ((msr.lo & 0xf) - 1); in cpu_set_power_limits()
668 msr = msr_read(MSR_PKG_POWER_SKU); in cpu_set_power_limits()
669 tdp = msr.lo & 0x7fff; in cpu_set_power_limits()
670 min_power = (msr.lo >> 16) & 0x7fff; in cpu_set_power_limits()
671 max_power = msr.hi & 0x7fff; in cpu_set_power_limits()
672 max_time = (msr.hi >> 16) & 0x7f; in cpu_set_power_limits()
707 msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO)); in cpu_set_power_limits()
708 msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI)); in cpu_set_power_limits()
709 msr_write(MSR_DDR_RAPL_LIMIT, msr); in cpu_set_power_limits()
713 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); in cpu_set_power_limits()
715 limit.lo = msr.lo & 0xff; in cpu_set_power_limits()
722 msr_t msr; in broadwell_get_info() local
724 msr = msr_read(IA32_PERF_CTL); in broadwell_get_info()
725 info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000; in broadwell_get_info()