Home
last modified time | relevance | path

Searched refs:mmMP0_SMN_C2PMSG_81 (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dpsp_v12_0.c82 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); in psp_v12_0_bootloader_load_sysdrv()
121 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); in psp_v12_0_bootloader_load_sos()
143 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v12_0_bootloader_load_sos()
144 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v12_0_bootloader_load_sos()
H A Dpsp_v3_1.c88 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); in psp_v3_1_bootloader_load_sysdrv()
127 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); in psp_v3_1_bootloader_load_sos()
149 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v3_1_bootloader_load_sos()
150 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v3_1_bootloader_load_sos()
H A Dpsp_v11_0.c172 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); in psp_v11_0_is_sos_alive()
253 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v11_0_bootloader_load_sos()
254 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v11_0_bootloader_load_sos()
H A Dsoc15.c581 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); in soc15_need_reset_on_resume()
843 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); in soc15_need_reset_on_init()
H A Dnv.c553 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); in nv_need_reset_on_init()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_12_0_0_offset.h126 #define mmMP0_SMN_C2PMSG_81 … macro
H A Dmp_10_0_offset.h126 #define mmMP0_SMN_C2PMSG_81 … macro
H A Dmp_9_0_offset.h126 #define mmMP0_SMN_C2PMSG_81 0x0091 macro
H A Dmp_11_0_8_offset.h126 #define mmMP0_SMN_C2PMSG_81 … macro
H A Dmp_11_0_offset.h126 #define mmMP0_SMN_C2PMSG_81 … macro
H A Dmp_11_5_0_offset.h126 #define mmMP0_SMN_C2PMSG_81 … macro
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsienna_cichlid_ppt.c2474 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); in sienna_cichlid_is_mode1_reset_supported()