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Searched refs:miim (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/drivers/net/mscc_eswitch/
H A Dmscc_miim.c24 static int mscc_miim_wait_ready(struct mscc_miim_dev *miim) in mscc_miim_wait_ready() argument
26 return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY, in mscc_miim_wait_ready()
32 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; in mscc_miim_read() local
36 ret = mscc_miim_wait_ready(miim); in mscc_miim_read()
42 miim->regs + MIIM_CMD); in mscc_miim_read()
44 ret = mscc_miim_wait_ready(miim); in mscc_miim_read()
48 val = readl(miim->regs + MIIM_DATA); in mscc_miim_read()
62 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; in mscc_miim_write() local
65 ret = mscc_miim_wait_ready(miim); in mscc_miim_write()
71 MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD); in mscc_miim_write()
H A Docelot_switch.c143 static struct mscc_miim_dev miim[NUM_PHY]; variable
147 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; in mscc_miim_reset() local
149 if (miim->phy_regs) { in mscc_miim_reset()
150 writel(0, miim->phy_regs + PHY_CFG); in mscc_miim_reset()
152 | PHY_CFG_ENA, miim->phy_regs + PHY_CFG); in mscc_miim_reset()
194 miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]); in ocelot_mdiobus_init()
195 miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]); in ocelot_mdiobus_init()
196 bus->priv = &miim[INTERNAL]; in ocelot_mdiobus_init()
H A Dluton_switch.c210 static struct mscc_miim_dev miim[NUM_PHY]; variable
247 miim[mdiobus_id].regs = ioremap(phy_base[mdiobus_id], in luton_mdiobus_init()
249 bus->priv = &miim[mdiobus_id]; in luton_mdiobus_init()
/openbmc/u-boot/drivers/net/
H A Dpch_gbe.c341 if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY) in pch_gbe_mdio_ready()
353 u32 miim; in pch_gbe_mdio_read() local
358 miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | in pch_gbe_mdio_read()
361 writel(miim, &mac_regs->miim); in pch_gbe_mdio_read()
366 return readl(&mac_regs->miim) & 0xffff; in pch_gbe_mdio_read()
373 u32 miim; in pch_gbe_mdio_write() local
378 miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | in pch_gbe_mdio_write()
381 writel(miim, &mac_regs->miim); in pch_gbe_mdio_write()
H A Dpch_gbe.h258 u32 miim; member
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,luton.dtsi219 compatible = "mscc,luton-miim";
H A Dmscc,ocelot.dtsi188 compatible = "mscc,ocelot-miim";
/openbmc/
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