| /openbmc/u-boot/arch/arm/mach-keystone/ |
| H A D | psc.c | 97 u32 mdctl; in psc_set_state() local
130 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_state()
131 mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state); in psc_set_state()
132 mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso); in psc_set_state()
133 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_state()
157 u32 mdctl; in psc_enable_module() local
160 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_enable_module()
161 if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON) in psc_enable_module()
175 u32 mdctl; in psc_disable_module() local
178 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_disable_module()
[all …]
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| /openbmc/u-boot/arch/arm/mach-davinci/ |
| H A D | psc.c | 35 dv_reg_p mdstat, mdctl, ptstat, ptcmd; in lpsc_transition() local
45 mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); in lpsc_transition()
54 mdctl = &psc_regs->psc0.mdctl[id]; in lpsc_transition()
61 mdctl = &psc_regs->psc1.mdctl[id]; in lpsc_transition()
73 writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl); in lpsc_transition()
92 writel(readl(mdctl) | 0x200, mdctl); in lpsc_transition()
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| H A D | dm365_lowlevel.c | 251 writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) & in dm365_vpss_sync_reset()
253 &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]); in dm365_vpss_sync_reset()
337 setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE); in dm365_psc_init()
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| /openbmc/linux/drivers/clk/keystone/ |
| H A D | gate.c | 74 u32 ptcmd, pdstat, pdctl, mdstat, mdctl, ptstat; in psc_config() local
77 mdctl = readl(control_base + MDCTL); in psc_config()
78 mdctl &= ~MDSTAT_STATE_MASK; in psc_config()
79 mdctl |= next_state; in psc_config()
82 mdctl &= ~MDCTL_LRESET; in psc_config()
83 writel(mdctl, control_base + MDCTL); in psc_config()
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| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | fsl_mmdc.c | 53 tmp = priv->mdctl & ~(MDCTL_SDE0 | MDCTL_SDE1); in mmdc_init()
54 out_be32(&mmdc->mdctl, tmp); in mmdc_init()
62 out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0); in mmdc_init()
64 out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1); in mmdc_init()
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| /openbmc/u-boot/board/Barix/ipam390/ |
| H A D | ipam390.c | 45 dv_reg_p mdstat, mdctl, ptstat, ptcmd; in dsp_lpsc_on() local
50 mdctl = &psc_regs->psc0.mdctl[id]; in dsp_lpsc_on()
60 *mdctl |= 0x03; in dsp_lpsc_on()
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| /openbmc/u-boot/board/davinci/da8xxevm/ |
| H A D | omapl138_lcdk.c | 262 dv_reg_p mdstat, mdctl, ptstat, ptcmd; in dsp_lpsc_on() local
267 mdctl = &psc_regs->psc0.mdctl[id]; in dsp_lpsc_on()
277 *mdctl |= 0x03; in dsp_lpsc_on()
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| H A D | da850evm.c | 104 dv_reg_p mdstat, mdctl, ptstat, ptcmd; in dsp_lpsc_on() local
109 mdctl = &psc_regs->psc0.mdctl[id]; in dsp_lpsc_on()
119 *mdctl |= 0x03; in dsp_lpsc_on()
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| /openbmc/u-boot/arch/arm/mach-imx/ |
| H A D | cpu.c | 110 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) argument
111 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7) argument
112 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3) argument
113 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) argument
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| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | ddr.c | 265 cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000; in mmdc_do_dqs_calibration()
266 cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000; in mmdc_do_dqs_calibration()
316 clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */ in mmdc_do_dqs_calibration()
318 clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */ in mmdc_do_dqs_calibration()
324 cs0_enable = readl(&mmdc0->mdctl) & 0x80000000; in mmdc_do_dqs_calibration()
325 cs1_enable = readl(&mmdc0->mdctl) & 0x40000000; in mmdc_do_dqs_calibration()
539 setbits_le32(&mmdc0->mdctl, 1 << 30); in mmdc_do_dqs_calibration()
543 setbits_le32(&mmdc0->mdctl, 1 << 31); in mmdc_do_dqs_calibration()
1165 mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */ in mx6_lpddr2_cfg()
1175 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */ in mx6_lpddr2_cfg()
[all …]
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| /openbmc/u-boot/include/ |
| H A D | fsl_mmdc.h | 67 u32 mdctl; member
153 u32 mdctl; member
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| /openbmc/u-boot/arch/arm/mach-davinci/include/mach/ |
| H A D | psc_defs.h | 49 unsigned int mdctl[52]; /* 0xA00 */ member
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| H A D | hardware.h | 344 dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT]; member
349 dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT]; member
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| /openbmc/u-boot/board/freescale/ls1012afrdm/ |
| H A D | ls1012afrdm.c | 132 mparam.mdctl = 0x05180000; in dram_init()
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| /openbmc/linux/drivers/clk/davinci/ |
| H A D | psc.c | 295 u32 mdctl; in davinci_lpsc_clk_reset() local
300 mdctl = reset ? 0 : MDCTL_LRESET; in davinci_lpsc_clk_reset()
301 regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_LRESET, mdctl); in davinci_lpsc_clk_reset()
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| /openbmc/u-boot/arch/arm/include/asm/arch-mx6/ |
| H A D | mx6-ddr.h | 39 u32 mdctl; member
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