Home
last modified time | relevance | path

Searched refs:mbar2_writeLong (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/m68k/cpu/mcf52x2/
H A Dcpu_init.c205 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); in cpu_init_f()
676 mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); in cpu_init_f()
677 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); in cpu_init_f()
678 mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); in cpu_init_f()
679 mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); in cpu_init_f()
680 mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); in cpu_init_f()
681 mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); in cpu_init_f()
707 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); in cpu_init_f()
710 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ in cpu_init_f()
716 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); in cpu_init_f()
[all …]
H A Dspeed.c47 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
48 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
/openbmc/u-boot/board/freescale/m5249evb/
H A Dm5249evb.c27 mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ in checkboard()
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5249.h22 #define mbar2_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y macro
/openbmc/u-boot/board/freescale/m5253demo/
H A Dm5253demo.c114 mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); in ide_set_reset()