/openbmc/linux/tools/testing/selftests/bpf/progs/ |
H A D | cpumask_success.c | 29 mask1 = create_cpumask(); in create_cpumask_set() 30 if (!mask1) in create_cpumask_set() 35 bpf_cpumask_release(mask1); in create_cpumask_set() 42 bpf_cpumask_release(mask1); in create_cpumask_set() 50 bpf_cpumask_release(mask1); in create_cpumask_set() 57 *out1 = mask1; in create_cpumask_set() 187 mask1 = create_cpumask(); in BPF_PROG() 188 if (!mask1) in BPF_PROG() 203 if (mask1) in BPF_PROG() 472 if (!mask1 || !mask2) in BPF_PROG() [all …]
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/openbmc/linux/sound/pci/ice1712/ |
H A D | wm8776.c | 135 .mask1 = WM8776_DACVOL_MASK, 145 .mask1 = WM8776_DAC_PL_LL, 153 .mask1 = WM8776_DAC_DZCEN, 161 .mask1 = WM8776_HPVOL_MASK, 171 .mask1 = WM8776_PWR_HPPD, 179 .mask1 = WM8776_VOL_HPZCEN, 187 .mask1 = WM8776_OUTMUX_AUX, 199 .mask1 = WM8776_DAC_IZD, 214 .mask1 = WM8776_DAC2_DEEMPH, 232 .mask1 = WM8776_ADC_MUTEL, [all …]
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H A D | wm8766.c | 36 .mask1 = WM8766_VOL_MASK, 47 .mask1 = WM8766_VOL_MASK, 58 .mask1 = WM8766_VOL_MASK, 67 .mask1 = WM8766_DAC2_MUTE1, 74 .mask1 = WM8766_DAC2_MUTE2, 81 .mask1 = WM8766_DAC2_MUTE3, 106 .mask1 = WM8766_DAC2_DEEMP1, 112 .mask1 = WM8766_DAC2_DEEMP2, 118 .mask1 = WM8766_DAC2_DEEMP3, 124 .mask1 = WM8766_DAC_IZD, [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/ |
H A D | dc_helper.c | 110 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in set_reg_field_values() argument 118 field_value1, mask1, shift1); in set_reg_field_values() 225 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_update_ex() argument 253 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_set_ex() argument 289 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get2() argument 299 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get3() argument 311 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get4() argument 325 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get5() argument 341 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get6() argument 542 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_indirect_reg_update_ex() argument [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dmub/src/ |
H A D | dmub_reg.c | 45 uint32_t mask1, uint32_t field_value1, in set_reg_field_values() argument 52 set_reg_field_value_masks(field_value_mask, field_value1, mask1, in set_reg_field_values() 73 uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_update() argument 80 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in dmub_reg_update() 90 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_set() argument 96 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in dmub_reg_set()
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/openbmc/linux/fs/orangefs/ |
H A D | orangefs-debugfs.c | 63 __u64 mask1; member 456 c_mask.mask1, in orangefs_debug_write() 543 (unsigned long long *)&(cdm_array[i].mask1), in orangefs_prepare_cdm_array() 755 if ((mask->mask1 & cdm_array[index].mask1) || in do_c_string() 799 if ((c_mask->mask1 == cdm_array[client_all_index].mask1) && in check_amalgam_keyword() 806 if ((c_mask->mask1 == cdm_array[client_verbose_index].mask1) && in check_amalgam_keyword() 875 (**sane_mask).mask1 = (**sane_mask).mask1 | cdm_array[i].mask1; in do_c_mask() 900 client_debug_mask.mask1 = mask2_info.mask1_value; in orangefs_debugfs_new_client_mask() 906 (unsigned long long)client_debug_mask.mask1, in orangefs_debugfs_new_client_mask()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
H A D | irq_service_dcn302.c | 195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 197 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 199 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 200 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument 216 reg1 ## __ ## mask1 ## _MASK,\ 218 reg1 ## __ ## mask1 ## _MASK,\ 219 ~reg1 ## __ ## mask1 ## _MASK \
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
H A D | irq_service_dcn21.c | 215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument 232 reg1 ## __ ## mask1 ## _MASK,\ 234 reg1 ## __ ## mask1 ## _MASK,\ 235 ~reg1 ## __ ## mask1 ## _MASK \
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
H A D | irq_service_dcn314.c | 210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 215 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 216 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument 227 reg1 ## __ ## mask1 ## _MASK,\ 229 reg1 ## __ ## mask1 ## _MASK,\ 230 ~reg1 ## __ ## mask1 ## _MASK \
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
H A D | irq_service_dcn315.c | 215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument 232 reg1 ## __ ## mask1 ## _MASK,\ 234 reg1 ## __ ## mask1 ## _MASK,\ 235 ~reg1 ## __ ## mask1 ## _MASK \
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
H A D | irq_service_dcn31.c | 208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 211 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument 225 reg1 ## __ ## mask1 ## _MASK,\ 227 reg1 ## __ ## mask1 ## _MASK,\ 228 ~reg1 ## __ ## mask1 ## _MASK \
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
H A D | irq_service_dcn32.c | 209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 215 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument 226 reg1 ## __ ## mask1 ## _MASK,\ 228 reg1 ## __ ## mask1 ## _MASK,\ 229 ~reg1 ## __ ## mask1 ## _MASK \
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
H A D | irq_service_dcn30.c | 220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 223 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 226 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument 237 reg1 ## __ ## mask1 ## _MASK,\ 239 reg1 ## __ ## mask1 ## _MASK,\ 240 ~reg1 ## __ ## mask1 ## _MASK \
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/openbmc/u-boot/arch/arm/mach-mvebu/ |
H A D | efuse.c | 69 struct efuse_val *new_val, u32 mask0, u32 mask1) in do_prog_efuse() argument 81 val.dwords.d[1] |= (new_val->dwords.d[1] & mask1); in do_prog_efuse() 94 static int prog_efuse(int nr, struct efuse_val *new_val, u32 mask0, u32 mask1) in prog_efuse() argument 118 if (!new_val->dwords.d[0] && !new_val->dwords.d[1] && (mask0 | mask1)) in prog_efuse() 123 res = do_prog_efuse(efuse, new_val, mask0, mask1); in prog_efuse()
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/openbmc/linux/arch/alpha/kernel/ |
H A D | sys_rawhide.c | 102 unsigned int mask, mask1, hose; in rawhide_mask_and_ack_irq() local 111 mask1 = 1 << irq; in rawhide_mask_and_ack_irq() 112 mask = ~mask1 | hose_irq_masks[hose]; in rawhide_mask_and_ack_irq() 121 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; in rawhide_mask_and_ack_irq()
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H A D | sys_titan.c | 69 unsigned long mask0, mask1, mask2, mask3, dummy; in titan_update_irq_hw() local 74 mask1 = mask & titan_cpu_irq_affinity[1]; in titan_update_irq_hw() 79 else if (bcpu == 1) mask1 |= isa_enable; in titan_update_irq_hw() 93 *dim1 = mask1; in titan_update_irq_hw()
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/openbmc/linux/arch/mips/sgi-ip27/ |
H A D | ip27-nmi.c | 134 u64 mask0, mask1, pend0, pend1; in nmi_dump_hub_irq() local 138 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A); in nmi_dump_hub_irq() 141 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B); in nmi_dump_hub_irq() 147 pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1); in nmi_dump_hub_irq()
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/openbmc/linux/drivers/soc/fsl/qe/ |
H A D | gpio.c | 241 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); in qe_pin_set_dedicated() local 260 if (sregs->cpdata & mask1) in qe_pin_set_dedicated() 261 qe_gc->cpdata |= mask1; in qe_pin_set_dedicated() 263 qe_gc->cpdata &= ~mask1; in qe_pin_set_dedicated() 266 qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1); in qe_pin_set_dedicated()
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/openbmc/linux/arch/parisc/kernel/ |
H A D | sys_parisc32.c | 28 compat_uint_t mask0, compat_uint_t mask1, compat_int_t dfd, in sys32_fanotify_mark() argument 32 ((__u64)mask1 << 32) | mask0, in sys32_fanotify_mark()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
H A D | irq_service_dce120.c | 103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 106 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 108 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 109 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
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/openbmc/linux/drivers/pcmcia/ |
H A D | tcic.c | 241 u_int mask1; in irq_scan() local 252 mask1 = 0; in irq_scan() 256 mask1 |= (1 << i); in irq_scan() 258 if ((mask1 & (1 << i)) && (try_irq(i) != 0)) { in irq_scan() 259 mask1 ^= (1 << i); in irq_scan() 263 if (mask1) { in irq_scan() 270 mask1 |= (1 << i); in irq_scan() 278 if (mask1 & (1<<i)) in irq_scan() 279 printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i); in irq_scan() 282 return mask1; in irq_scan()
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/openbmc/linux/drivers/net/hamradio/ |
H A D | hdlcdrv.c | 159 unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; in hdlcdrv_receiver() local 177 for(i = 15, mask1 = 0x1fc00, mask2 = 0x1fe00, mask3 = 0x0fc00, in hdlcdrv_receiver() 180 i--, mask1 <<= 1, mask2 <<= 1, mask3 <<= 1, mask4 <<= 1, in hdlcdrv_receiver() 182 if ((s->hdlcrx.bitstream & mask1) == mask1) in hdlcdrv_receiver() 255 unsigned int mask1, mask2, mask3; in hdlcdrv_transmitter() local 330 mask1 = 0x1f000; in hdlcdrv_transmitter() 334 for(i = 0; i < 8; i++, mask1 <<= 1, mask2 <<= 1, in hdlcdrv_transmitter() 336 if ((s->hdlctx.bitstream & mask1) != mask1) in hdlcdrv_transmitter()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
H A D | irq_service_dcn303.c | 119 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 121 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 123 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 124 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
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/openbmc/linux/include/linux/ |
H A D | cpumask.h | 332 #define for_each_cpu_and(cpu, mask1, mask2) \ argument 333 for_each_and_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits) 350 #define for_each_cpu_andnot(cpu, mask1, mask2) \ argument 351 for_each_andnot_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits) 367 #define for_each_cpu_or(cpu, mask1, mask2) \ argument 368 for_each_or_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits) 758 #define cpumask_any_and(mask1, mask2) cpumask_first_and((mask1), (mask2)) argument
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/openbmc/linux/lib/ |
H A D | cpumask_kunit.c | 26 #define EXPECT_FOR_EACH_CPU_OP_EQ(test, op, mask1, mask2) \ argument 28 const cpumask_t *m1 = (mask1); \ 34 for_each_cpu_##op(cpu, mask1, mask2) \
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