Searched refs:lane_cnt (Results 1 – 14 of 14) sorted by relevance
54 u8 lane_cnt; in dp501_link_training() local68 lane_cnt = 4; in dp501_link_training()70 lane_cnt = max_lane_cnt; in dp501_link_training()71 if (lane_cnt != max_lane_cnt) in dp501_link_training()73 max_lane_cnt, lane_cnt); in dp501_link_training()74 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
259 u8 lane_cnt; member561 u8 lane_cnt; in zynqmp_dp_mode_configure() local580 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) { in zynqmp_dp_mode_configure()588 dp->mode.lane_cnt = lane_cnt; in zynqmp_dp_mode_configure()648 dp->mode.lane_cnt); in zynqmp_dp_update_vs_emph()680 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_link_train_cr() local715 if (i == lane_cnt) in zynqmp_dp_link_train_cr()746 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_link_train_ce() local796 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_train() local1228 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_encoder_mode_set_stream() local[all …]
176 unsigned char lane_cnt[16]; in exynos_dp_handle_edid() local180 memset(lane_cnt, 0, 16); in exynos_dp_handle_edid()229 priv->lane_cnt = temp; in exynos_dp_handle_edid()285 buf[1] = priv->lane_cnt; in exynos_dp_link_start()294 priv->lane_cnt); in exynos_dp_link_start()402 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_read_dpcd_lane_stat()508 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_process_clock_recovery()543 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_process_clock_recovery()627 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_process_equalizer_training()676 for (i = 0; i < priv->lane_cnt; i++) in exynos_dp_process_equalizer_training()[all …]
342 u8 lane_cnt = csid->phy.lane_cnt; in __csid_configure_stream() local348 if (!lane_cnt) in __csid_configure_stream()349 lane_cnt = 4; in __csid_configure_stream()449 val |= (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES; in __csid_configure_stream()455 val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; in __csid_configure_stream()
87 u8 lane_cnt; member
217 val = phy->lane_cnt - 1; in csid_configure_stream()
246 val = phy->lane_cnt - 1; in csid_configure_stream()
98 csid->phy.lane_cnt); in csid_set_clock_rates()767 csid->phy.lane_cnt = lane_cfg->num_data; in csid_link_setup()
25 for (i = 0; i < (phy)->lane_cnt; i++)155 ss_phy->lane_cnt = phy->attrs.bus_width; in samsung_ufs_phy_init()283 phy->lane_cnt = PHY_DEF_LANE_CNT; in samsung_ufs_phy_probe()
125 u8 lane_cnt; member
70 unsigned char lane_cnt; member
140 u16 lane_cnt:2; member
833 intel_dsi->lane_count = mipi_config->lane_cnt + 1; in intel_dsi_vbt_init()
1007 int ret = 0, lane, lane_cnt; in dp_ctrl_update_vx_px() local1038 lane_cnt = ctrl->link->link_params.num_lanes; in dp_ctrl_update_vx_px()1039 for (lane = 0; lane < lane_cnt; lane++) in dp_ctrl_update_vx_px()1046 buf, lane_cnt); in dp_ctrl_update_vx_px()1047 if (ret == lane_cnt) in dp_ctrl_update_vx_px()