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/openbmc/linux/drivers/phy/freescale/
H A Dphy-fsl-lynx-28g.c47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
62 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
99 #define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4) argument
104 #define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10) argument
153 lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
156 ioread32((lane)->priv->base + LYNX_28G_##reg((lane)->id))
517 lane = &priv->lane[i]; in lynx_28g_cdr_lock_check()
521 if (!lane->init || !lane->powered_up) { in lynx_28g_cdr_lock_check()
589 struct lynx_28g_lane *lane = &priv->lane[i]; in lynx_28g_probe() local
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/openbmc/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c522 lane->id, lane->mode, old, new); in mvebu_a3700_comphy_set_phy_selector()
527 lane->mode); in mvebu_a3700_comphy_set_phy_selector()
673 lane->submode, lane->id); in mvebu_a3700_comphy_ethernet_power_on()
781 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
806 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
815 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
1123 if (mvebu_a3700_comphy_modes[i].lane == lane && in mvebu_a3700_comphy_check_mode()
1147 (lane->mode != mode || lane->submode != submode)) in mvebu_a3700_comphy_set_mode()
1161 if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode, in mvebu_a3700_comphy_power_on()
1172 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id); in mvebu_a3700_comphy_power_on()
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H A Dphy-mvebu-cp110-comphy.c182 unsigned lane; member
309 if (conf->lane == lane && in mvebu_comphy_get_mode()
381 lane->id); in mvebu_comphy_ethernet_init_reset()
402 lane->id); in mvebu_comphy_ethernet_init_reset()
729 mux = mvebu_comphy_get_mux(lane->id, lane->port, in mvebu_comphy_power_on_legacy()
730 lane->mode, lane->submode); in mvebu_comphy_power_on_legacy()
774 fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port, in mvebu_comphy_power_on()
775 lane->mode, lane->submode); in mvebu_comphy_power_on()
785 lane->id); in mvebu_comphy_power_on()
790 lane->id); in mvebu_comphy_power_on()
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H A Dphy-armada38x-comphy.c67 conf |= BIT(lane->port); in a38x_set_conf()
69 conf &= ~BIT(lane->port); in a38x_set_conf()
103 dev_err(lane->priv->dev, in a38x_comphy_poll()
136 a38x_set_conf(lane, false); in a38x_comphy_set_mode()
147 a38x_set_conf(lane, true); in a38x_comphy_set_mode()
172 if (lane->port >= 0) in a38x_comphy_xlate()
175 lane->port = args->args[0]; in a38x_comphy_xlate()
180 if (!gbe_mux[lane->n][lane->port] || in a38x_comphy_xlate()
181 val != gbe_mux[lane->n][lane->port]) { in a38x_comphy_xlate()
182 dev_warn(lane->priv->dev, in a38x_comphy_xlate()
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/openbmc/linux/drivers/net/dsa/b53/
H A Db53_serdes.c44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config() local
92 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_an_restart() local
106 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_get_state() local
173 switch (lane) { in b53_serdes_phylink_get_caps()
200 if (lane == B53_INVALID_LANE || lane >= B53_N_PCS || in b53_serdes_phylink_mac_select_pcs()
201 !dev->pcs[lane].dev) in b53_serdes_phylink_mac_select_pcs()
238 pcs = &dev->pcs[lane]; in b53_serdes_init()
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/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c349 if (lane == 2) in usb3_reg_set16()
453 lane); in comphy_usb3_power_up()
479 | 0x20, 0xFFFF, lane); in comphy_usb3_power_up()
485 if (lane == 2) { in comphy_usb3_power_up()
716 reg_set(COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
970 u32 lane, ret = 0; in comphy_a3700_init() local
978 for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count; in comphy_a3700_init()
979 lane++, comphy_map++) { in comphy_a3700_init()
996 ret = comphy_usb3_power_up(lane, in comphy_a3700_init()
1010 lane); in comphy_a3700_init()
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H A Dcomphy_mux.c23 int lane, opt, valid; in comphy_mux_check_config() local
27 for (lane = 0; lane < comphy_max_lanes; in comphy_mux_check_config()
28 lane++, comphy_map_data++, mux_data++) { in comphy_mux_check_config()
43 lane, comphy_map_data->type); in comphy_mux_check_config()
44 debug("set lane %d as type %d\n", lane, in comphy_mux_check_config()
49 lane, comphy_map_data->type); in comphy_mux_check_config()
57 u32 type, int lane) in comphy_mux_get_mux_value() argument
84 u32 lane, value, offset, mask; in comphy_mux_reg_write() local
88 for (lane = 0; lane < comphy_max_lanes; in comphy_mux_reg_write()
100 offset = lane * bitcount; in comphy_mux_reg_write()
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H A Dcomphy_core.c54 u32 lane; in comphy_print() local
56 for (lane = 0; lane < chip_cfg->comphy_lanes_count; in comphy_print()
57 lane++, comphy_map_data++) { in comphy_print()
59 printf("Comphy-%d: %-13s\n", lane, in comphy_print()
62 printf("Comphy-%d: %-13s %-10s\n", lane, in comphy_print()
81 int lane; in comphy_probe() local
128 lane = 0; in comphy_probe()
134 comphy_map_data[lane].speed = fdtdec_get_int( in comphy_probe()
136 comphy_map_data[lane].type = fdtdec_get_int( in comphy_probe()
146 lane + 1); in comphy_probe()
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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c189 int lane; in serdes_get_bank_by_device() local
193 return lane; in serdes_get_bank_by_device()
201 int lane; in __serdes_get_lane_count() local
203 for (lane = first; lane < SRDS_MAX_LANES; lane++) { in __serdes_get_lane_count()
208 return lane - first; in __serdes_get_lane_count()
496 int lane, bank, idx; in fsl_serdes_init() local
571 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in fsl_serdes_init()
666 unsigned int lane; in fsl_serdes_init() local
668 for (lane = 0; lane < SRDS_MAX_LANES; lane++) in fsl_serdes_init()
686 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in fsl_serdes_init()
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H A Dp1010_serdes.c57 int lane; in fsl_serdes_init() local
69 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
70 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
82 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
83 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_fixed_vs_pe_retimer.c52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
80 uint8_t lane = 0; in dp_fixed_vs_pe_set_retimer_lane_settings() local
82 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
84 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
86 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
168 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in perform_fixed_vs_pe_nontransparent_training_sequence()
368 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence_legacy()
467 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence_legacy()
714 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence()
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H A Dlink_dp_training.c343 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in maximize_lane_settings()
357 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_hw_to_dpcd_lane_settings()
462 for (lane = 0; lane < in dp_is_max_vs_reached()
479 for (lane = 0; lane < (uint32_t)(ln_count); lane++) { in dp_is_cr_done()
492 for (lane = 0; lane < (uint32_t)(ln_count); lane++) in dp_is_ch_eq_done()
503 for (lane = 0; lane < (uint32_t)(ln_count); lane++) in dp_is_symbol_locked()
591 for (lane = 0; lane < in dp_get_lane_status_and_lane_adjust()
653 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in override_lane_settings()
709 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in override_training_settings()
817 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_decide_lane_settings()
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/openbmc/u-boot/board/highbank/
H A Dahci.c84 tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_spread_spectrum_override()
96 static void cphy_tx_attenuation_override(u8 phy, u8 lane) in cphy_tx_attenuation_override() argument
102 shift = ((phy == 5) ? 4 : lane) * 4; in cphy_tx_attenuation_override()
109 tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_tx_attenuation_override()
123 u8 lane = 0, phy = 0; in cphy_disable_port_overrides() local
128 lane = port - 1; in cphy_disable_port_overrides()
155 u8 lane = 0, phy = 0; in cphy_override_lane() local
160 lane = port - 1; in cphy_override_lane()
166 lane * SPHY_LANE); in cphy_override_lane()
168 cphy_spread_spectrum_override(phy, lane, 3); in cphy_override_lane()
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/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dserdes.c244 int lane = -ENODEV; in mv88e6341_serdes_get_lane() local
255 return lane; in mv88e6341_serdes_get_lane()
261 int lane = -ENODEV; in mv88e6390_serdes_get_lane() local
278 return lane; in mv88e6390_serdes_get_lane()
353 return lane; in mv88e6390x_serdes_get_lane()
373 lane = port; in mv88e6393x_serdes_get_lane()
375 return lane; in mv88e6393x_serdes_get_lane()
436 int lane; in mv88e6390_serdes_get_stats() local
440 if (lane < 0) in mv88e6390_serdes_get_stats()
495 int lane; in mv88e6390_serdes_get_regs() local
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/openbmc/linux/drivers/phy/tegra/
H A Dxusb.c143 lane->pad->ops->remove(lane); in tegra_xusb_lane_destroy()
331 lane->pad->ops->iddq_enable(lane); in tegra_xusb_lane_program()
340 lane->pad->ops->iddq_disable(lane); in tegra_xusb_lane_program()
394 const char *func = lane->soc->funcs[lane->function]; in tegra_xusb_lane_check()
412 hit = lane; in tegra_xusb_find_lane()
444 match = lane; in tegra_xusb_port_find_lane()
1398 return lane->pad->ops->enable_phy_sleepwalk(lane, speed); in tegra_xusb_padctl_enable_phy_sleepwalk()
1409 return lane->pad->ops->disable_phy_sleepwalk(lane); in tegra_xusb_padctl_disable_phy_sleepwalk()
1420 return lane->pad->ops->enable_phy_wake(lane); in tegra_xusb_padctl_enable_phy_wake()
1431 return lane->pad->ops->disable_phy_wake(lane); in tegra_xusb_padctl_disable_phy_wake()
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H A Dxusb.h63 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
76 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
86 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
105 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
115 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
125 to_sata_lane(struct tegra_xusb_lane *lane) in to_sata_lane() argument
134 void (*remove)(struct tegra_xusb_lane *lane);
135 void (*iddq_enable)(struct tegra_xusb_lane *lane);
136 void (*iddq_disable)(struct tegra_xusb_lane *lane);
139 int (*enable_phy_wake)(struct tegra_xusb_lane *lane);
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H A Dxusb-tegra210.c455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
1699 struct tegra_xusb_lane *lane; in tegra210_usb3_set_lfps_detect() local
1706 lane = port->lane; in tegra210_usb3_set_lfps_detect()
1919 lane->index); in tegra210_usb2_phy_set_mode()
2123 lane->index); in tegra210_usb2_phy_power_off()
2567 if (!lane || !lane->pad || !lane->pad->padctl) in tegra210_lane_to_usb3_port()
3089 struct tegra_xusb_lane *lane; in tegra210_utmi_port_reset() local
3092 lane = phy_get_drvdata(phy); in tegra210_utmi_port_reset()
3093 padctl = lane->pad->padctl; in tegra210_utmi_port_reset()
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/openbmc/u-boot/board/freescale/p2041rdb/
H A Deth.c94 if (lane < 0) in board_ft_fman_fixup_port()
96 slot = lane_to_slot[lane]; in board_ft_fman_fixup_port()
112 int lane = serdes_get_first_lane(XAUI_FM1); in board_ft_fman_fixup_port() local
113 if (lane >= 0) { in board_ft_fman_fixup_port()
115 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); in board_ft_fman_fixup_port()
128 int lane; in board_eth_init() local
164 if (lane < 0) in board_eth_init()
166 slot = lane_to_slot[lane]; in board_eth_init()
186 lane = serdes_get_first_lane(XAUI_FM1); in board_eth_init()
187 if (lane >= 0) { in board_eth_init()
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/openbmc/linux/drivers/phy/
H A Dphy-xgene.c689 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
691 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
699 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
701 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
944 int lane; in xgene_phy_sata_cfg_lanes() local
946 for (lane = 0; lane < MAX_LANE; lane++) { in xgene_phy_sata_cfg_lanes()
961 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
989 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
992 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
995 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy_regs.h19 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
84 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) argument
85 #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28)) argument
86 #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24)) argument
91 #define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \ argument
122 #define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4)) argument
123 #define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4)) argument
124 #define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4)) argument
125 #define XELPDP_LANE_PCLK_REFCLK_ACK(lane) REG_BIT(28 - ((lane) * 4)) argument
172 #define PHY_CX0_VDROVRD_CTL(lane, tx, control) \ argument
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/openbmc/u-boot/board/freescale/corenet_ds/
H A Deth_superhydra.c217 int lane, slot, phy; in board_ft_fman_fixup_port() local
299 int lane, slot; in fdt_fixup_board_enet() local
307 if (lane >= 0) { in fdt_fixup_board_enet()
327 if (lane >= 0) { in fdt_fixup_board_enet()
343 if (lane >= 0) { in fdt_fixup_board_enet()
363 if (lane >= 0) { in fdt_fixup_board_enet()
422 int lane; in board_eth_init() local
519 if (lane < 0) in board_eth_init()
636 if (lane >= 0) { in board_eth_init()
654 if (lane < 0) in board_eth_init()
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/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dmpc8610_serdes.c54 int lane; in fsl_serdes_init() local
66 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
67 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
79 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
80 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
H A Dmpc8641_serdes.c63 int lane; in fsl_serdes_init() local
75 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
76 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
88 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
89 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
/openbmc/u-boot/board/freescale/t1040qds/
H A Deth.c302 if (lane < 0) in board_ft_fman_fixup_port()
317 int i, lane, idx; in fdt_fixup_board_enet() local
325 if (lane < 0) in fdt_fixup_board_enet()
374 if (lane < 0) in t1040_handle_phy_interface_sgmii()
443 int lane; in board_eth_init() local
504 lane = -1; in board_eth_init()
514 if (lane >= 0) { in board_eth_init()
523 if (lane < 0) in board_eth_init()
540 if (lane >= 0) { in board_eth_init()
549 if (lane >= 0) { in board_eth_init()
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/openbmc/u-boot/arch/arm/mach-tegra/
H A Dxusb-padctl-common.c139 for (i = 0; i < lane->num_funcs; i++) in tegra_xusb_padctl_lane_find_function()
140 if (lane->funcs[i] == func) in tegra_xusb_padctl_lane_find_function()
153 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_group_apply() local
158 if (!lane) { in tegra_xusb_padctl_group_apply()
167 group->func, lane->name, func); in tegra_xusb_padctl_group_apply()
171 value = padctl_readl(padctl, lane->offset); in tegra_xusb_padctl_group_apply()
174 value &= ~(lane->mask << lane->shift); in tegra_xusb_padctl_group_apply()
175 value |= func << lane->shift; in tegra_xusb_padctl_group_apply()
181 if (lane->iddq > 0 && group->iddq >= 0) { in tegra_xusb_padctl_group_apply()
183 value &= ~(1 << lane->iddq); in tegra_xusb_padctl_group_apply()
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