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/openbmc/u-boot/arch/arm/dts/
H A Dexynos4x12-pinctrl.dtsi21 interrupt-controller;
22 #interrupt-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
37 interrupt-controller;
38 #interrupt-cells = <2>;
45 interrupt-controller;
46 #interrupt-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
[all …]
H A Dexynos5250-pinctrl.dtsi21 interrupt-controller;
22 #interrupt-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
37 interrupt-controller;
38 #interrupt-cells = <2>;
45 interrupt-controller;
46 #interrupt-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
[all …]
H A Dexynos54xx-pinctrl.dtsi23 interrupt-controller;
24 #interrupt-cells = <2>;
31 interrupt-controller;
32 interrupt-parent = <&combiner>;
33 #interrupt-cells = <2>;
42 interrupt-controller;
43 interrupt-parent = <&combiner>;
44 #interrupt-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
[all …]
H A Dexynos4210-pinctrl.dtsi23 interrupt-controller;
24 #interrupt-cells = <2>;
31 interrupt-controller;
32 #interrupt-cells = <2>;
39 interrupt-controller;
40 #interrupt-cells = <2>;
47 interrupt-controller;
48 #interrupt-cells = <2>;
55 interrupt-controller;
56 #interrupt-cells = <2>;
[all …]
H A Dexynos4.dtsi23 combiner: interrupt-controller@10440000 {
25 #interrupt-cells = <2>;
26 interrupt-controller;
30 gic: interrupt-controller@10490000 {
32 #interrupt-cells = <3>;
33 interrupt-controller;
73 interrupt-parent = <&gic>;
82 interrupt-parent = <&gic>;
91 interrupt-parent = <&gic>;
100 interrupt-parent = <&gic>;
[all …]
H A Dstm32mp157-pinctrl.dtsi15 interrupt-parent = <&exti>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
34 interrupt-controller;
35 #interrupt-cells = <2>;
46 interrupt-controller;
47 #interrupt-cells = <2>;
58 interrupt-controller;
59 #interrupt-cells = <2>;
70 interrupt-controller;
[all …]
H A Dzynqmp.dtsi107 interrupt-parent = <&gic>;
122 interrupt-parent = <&gic>;
128 interrupt-parent = <&gic>;
219 gic: interrupt-controller@f9010000 {
221 #interrupt-cells = <3>;
226 interrupt-controller;
227 interrupt-parent = <&gic>;
245 interrupt-parent = <&gic>;
256 interrupt-parent = <&gic>;
271 interrupt-parent = <&gic>;
[all …]
H A Dkeystone-k2e.dtsi16 interrupt-parent = <&gic>;
103 #interrupt-cells = <1>;
104 interrupt-map-mask = <0 0 0 7>;
105 interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
110 pcie_msi_intc1: msi-interrupt-controller {
111 interrupt-controller;
112 #interrupt-cells = <1>;
113 interrupt-parent = <&gic>;
124 pcie_intc1: legacy-interrupt-controller {
125 interrupt-controller;
[all …]
H A Dzynq-7000.dtsi51 interrupt-parent = <&intc>;
70 interrupt-parent = <&intc>;
77 interrupt-parent = <&intc>;
88 interrupt-parent = <&intc>;
100 interrupt-parent = <&intc>;
110 interrupt-controller;
111 #interrupt-cells = <2>;
112 interrupt-parent = <&intc>;
121 interrupt-parent = <&intc>;
132 interrupt-parent = <&intc>;
[all …]
H A Darmada-xp-mv78260.dtsi138 #interrupt-cells = <1>;
142 interrupt-map-mask = <0 0 0 0>;
143 interrupt-map = <0 0 0 0 &mpic 58>;
156 #interrupt-cells = <1>;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 59>;
174 #interrupt-cells = <1>;
178 interrupt-map-mask = <0 0 0 0>;
179 interrupt-map = <0 0 0 0 &mpic 60>;
192 #interrupt-cells = <1>;
[all …]
H A Darmada-xp-mv78460.dtsi159 #interrupt-cells = <1>;
163 interrupt-map-mask = <0 0 0 0>;
164 interrupt-map = <0 0 0 0 &mpic 58>;
177 #interrupt-cells = <1>;
181 interrupt-map-mask = <0 0 0 0>;
182 interrupt-map = <0 0 0 0 &mpic 59>;
195 #interrupt-cells = <1>;
199 interrupt-map-mask = <0 0 0 0>;
200 interrupt-map = <0 0 0 0 &mpic 60>;
213 #interrupt-cells = <1>;
[all …]
H A Dbcm2836.dtsi14 interrupt-controller;
15 #interrupt-cells = <1>;
16 interrupt-parent = <&local_intc>;
21 interrupt-parent = <&local_intc>;
28 interrupt-parent = <&local_intc>;
71 /* Make the BCM2835-style global interrupt controller be a child of the
72 * CPU-local interrupt controller.
77 interrupt-parent = <&local_intc>;
H A Dimx53.dtsi19 #include <dt-bindings/interrupt-controller/irq.h>
38 tzic: tz-interrupt-controller@fffc000 {
40 interrupt-controller;
41 #interrupt-cells = <1>;
49 interrupt-parent = <&tzic>;
126 interrupt-controller;
127 #interrupt-cells = <2>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
146 interrupt-controller;
[all …]
H A Dexynos4210.dtsi40 gic: interrupt-controller@10490000 {
47 interrupt-parent = <&mct_map>;
53 #interrupt-cells = <1>;
56 interrupt-map = <0 &gic 0 57 0>,
73 interrupt-parent = <&combiner>;
80 interrupt-parent = <&gic>;
87 interrupt-parent = <&gic>;
90 wakup_eint: wakeup-interrupt-controller {
92 interrupt-parent = <&gic>;
104 interrupt-parent = <&combiner>;
[all …]
H A Dexynos4x12.dtsi46 interrupt-parent = <&mct_map>;
52 #interrupt-cells = <1>;
55 interrupt-map = <0 &gic 0 57 0>,
66 interrupt-parent = <&gic>;
73 interrupt-parent = <&gic>;
76 wakup_eint: wakeup-interrupt-controller {
78 interrupt-parent = <&gic>;
86 interrupt-parent = <&combiner>;
93 interrupt-parent = <&gic>;
100 interrupt-parent = <&gic>;
H A Dhi3798cv200.dtsi12 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
60 gic: interrupt-controller@f1001000 {
65 #interrupt-cells = <3>;
66 interrupt-controller;
336 interrupt-controller;
337 #interrupt-cells = <2>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
370 interrupt-controller;
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dimg,boston.dts5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/interrupt-controller/mips-gic.h>
34 gic: interrupt-controller {
37 interrupt-controller;
38 #interrupt-cells = <3>;
55 #interrupt-cells = <1>;
57 interrupt-parent = <&gic>;
63 interrupt-map-mask = <0 0 0 7>;
64 interrupt-map = <0 0 0 1 &pci0_intc 0>,
69 pci0_intc: interrupt-controller {
[all …]
H A Dmt7628a.dtsi24 cpuintc: interrupt-controller {
26 #interrupt-cells = <1>;
27 interrupt-controller;
28 compatible = "mti,cpu-interrupt-controller";
58 interrupt-parent = <&intc>;
62 intc: interrupt-controller@200 {
66 interrupt-controller;
67 #interrupt-cells = <1>;
72 interrupt-parent = <&cpuintc>;
92 interrupt-parent = <&intc>;
[all …]
H A Djz4780.dtsi10 cpuintc: interrupt-controller {
12 #interrupt-cells = <1>;
13 interrupt-controller;
14 compatible = "mti,cpu-interrupt-controller";
17 intc: interrupt-controller@10001000 {
21 interrupt-controller;
22 #interrupt-cells = <1>;
24 interrupt-parent = <&cpuintc>;
74 interrupt-parent = <&intc>;
88 interrupt-parent = <&intc>;
[all …]
/openbmc/u-boot/arch/riscv/dts/
H A Dae350_32.dts33 CPU0_intc: interrupt-controller {
34 #interrupt-cells = <1>;
35 interrupt-controller;
52 plic0: interrupt-controller@e4000000 {
55 #interrupt-cells = <1>;
56 interrupt-controller;
62 plic1: interrupt-controller@e6400000 {
65 #interrupt-cells = <1>;
66 interrupt-controller;
90 interrupt-parent = <&plic0>;
[all …]
H A Dae350_64.dts33 CPU0_intc: interrupt-controller {
34 #interrupt-cells = <1>;
35 interrupt-controller;
52 plic0: interrupt-controller@e4000000 {
55 #interrupt-cells = <2>;
56 interrupt-controller;
62 plic1: interrupt-controller@e6400000 {
65 #interrupt-cells = <2>;
66 interrupt-controller;
90 interrupt-parent = <&plic0>;
[all …]
/openbmc/qemu/pc-bios/dtb/
H A Dcanyonlands.dts52 UIC0: interrupt-controller0 {
54 interrupt-controller;
59 #interrupt-cells = <2>;
62 UIC1: interrupt-controller1 {
64 interrupt-controller;
69 #interrupt-cells = <2>;
71 interrupt-parent = <&UIC0>;
74 UIC2: interrupt-controller2 {
76 interrupt-controller;
81 #interrupt-cells = <2>;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dgpio-pcf857x.txt46 an interrupt controller. When the expander interrupt line is connected all the
48 interrupt controller device tree bindings documentation available at
49 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
51 - interrupt-controller: Identifies the node as an interrupt controller.
52 - #interrupt-cells: Number of cells to encode an interrupt source, shall be 2.
53 - interrupt-parent: phandle of the parent interrupt controller.
54 - interrupts: Interrupt specifier for the controllers interrupt.
65 interrupt-parent = <&irqpin2>;
69 interrupt-controller;
70 #interrupt-cells = <2>;
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_timer.S66 rsr a2, interrupt
77 rsr a3, interrupt
83 rsr a2, interrupt
91 rsr a2, interrupt
104 rsr a3, interrupt
106 rsr a5, interrupt
119 rsr a2, interrupt
133 rsr a2, interrupt
156 rsr a2, interrupt
168 rsr a2, interrupt
[all …]
/openbmc/qemu/docs/specs/
H A Dedu.rst63 raise interrupt after finishing factorial computation
65 0x24 (RO) : interrupt status register
66 It contains values which raised the interrupt (see interrupt raise
69 0x60 (WO) : interrupt raise register
70 Raise an interrupt. The value will be put to the interrupt status
73 0x64 (WO) : interrupt acknowledge register
74 Clear an interrupt. The value will be cleared from the interrupt
95 raise interrupt 0x100 after finishing the DMA
100 An IRQ is generated when written to the interrupt raise register. The value
101 appears in interrupt status register when the interrupt is raised and has to
[all …]

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