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Searched refs:intenable (Results 1 – 25 of 25) sorted by relevance

/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_timer.S65 wsr a2, intenable
90 wsr a2, intenable
118 wsr a2, intenable
137 wsr a2, intenable
155 wsr a2, intenable
171 wsr a2, intenable
190 wsr a2, intenable
204 wsr a2, intenable
222 wsr a2, intenable
242 wsr a2, intenable
[all …]
H A Dtest_interrupt.S47 wsr a2, intenable
126 wsr a2, intenable
144 wsr a2, intenable
163 wsr a2, intenable
182 wsr a2, intenable
202 wsr a2, intenable
227 wsr a2, intenable
H A Dtest_sr.S150 test_sr intenable, 1
/openbmc/u-boot/drivers/net/
H A Ddesignware.h73 u32 intenable; /* 0x1c */ member
H A Dlpc32xx_eth.c129 u32 intenable; member
517 writel(0, &regs->intenable); in lpc32xx_eth_init()
H A Dcalxedaxgmac.c199 u32 intenable; member
/openbmc/qemu/target/xtensa/core-lx106/
H A Dgdb-config.c.inc63 XTREG( 40,160,15, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc6280 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
6283 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
6286 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dgdb-config.c.inc201 XTREG(90, 360, 22, 4, 4, 0x02e4, 0x0007, -2, 2, 0x1000, intenable,
H A Dxtensa-modules.c.inc11698 { "rsr.intenable", 213 /* xt_iclass_rsr.intenable */,
11701 { "wsr.intenable", 214 /* xt_iclass_wsr.intenable */,
11704 { "xsr.intenable", 215 /* xt_iclass_xsr.intenable */,
12423 return 317; /* xsr.intenable */
12621 return 315; /* rsr.intenable */
12758 return 316; /* wsr.intenable */
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dgdb-config.c.inc99 XTREG( 75,300,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc9285 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
9288 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
9291 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dgdb-config.c.inc116 XTREG(91, 364, 22, 4, 4, 0x02e4, 0x0007, -2, 2, 0x1000, intenable, 0, 0, 0, 0, 0, 0)
H A Dxtensa-modules.c.inc12347 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
12350 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
12353 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dgdb-config.c.inc113 XTREG( 78,360,12, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc27320 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
27323 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
27326 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
/openbmc/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc108 XTREG( 84,336,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc11716 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
11719 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
11722 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dgdb-config.c.inc145 XTREG(110,488,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc33866 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
33869 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
33872 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dgdb-config.c.inc149 XTREG(110,504,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc16975 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
16978 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
16981 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
/openbmc/qemu/target/xtensa/core-fsf/
H A Dxtensa-modules.c.inc8292 { "rsr.intenable", 151 /* xt_iclass_rsr.intenable */,
8295 { "wsr.intenable", 152 /* xt_iclass_wsr.intenable */,
8298 { "xsr.intenable", 153 /* xt_iclass_xsr.intenable */,
8884 return 195; /* xsr.intenable */
9029 return 193; /* rsr.intenable */
9128 return 194; /* wsr.intenable */
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dgdb-config.c.inc283 XTREG(204,1936,13, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc75950 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
75953 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
75956 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,