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Searched refs:intel_de_posting_read (Results 1 – 25 of 31) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_fdi.c307 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1); in cpt_set_fdi_bc_bifurcation()
366 intel_de_posting_read(dev_priv, reg); in intel_fdi_normal_train()
419 intel_de_posting_read(dev_priv, reg); in ilk_fdi_link_train()
447 intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe)); in ilk_fdi_link_train()
501 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
530 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
536 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); in gen6_fdi_link_train()
581 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
587 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); in gen6_fdi_link_train()
639 intel_de_posting_read(dev_priv, reg); in ivb_manual_fdi_link_train()
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H A Dg4x_hdmi.c61 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in intel_hdmi_prepare()
231 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in g4x_hdmi_enable_port()
269 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
271 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
284 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
291 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
293 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
338 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in cpt_enable_hdmi()
345 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in cpt_enable_hdmi()
385 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in intel_disable_hdmi()
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H A Dg4x_dp.c211 intel_de_posting_read(dev_priv, DP_A); in ilk_edp_pll_on()
226 intel_de_posting_read(dev_priv, DP_A); in ilk_edp_pll_on()
245 intel_de_posting_read(dev_priv, DP_A); in ilk_edp_pll_off()
433 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_link_down()
437 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_link_down()
457 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_link_down()
461 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_link_down()
586 intel_de_posting_read(dev_priv, intel_dp->output_reg); in cpt_set_link_train()
614 intel_de_posting_read(dev_priv, intel_dp->output_reg); in g4x_set_link_train()
638 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_enable_port()
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H A Dintel_fifo_underrun.c107 intel_de_posting_read(dev_priv, reg); in i9xx_check_fifo_underruns()
127 intel_de_posting_read(dev_priv, reg); in i9xx_set_fifo_underrun_reporting()
160 intel_de_posting_read(dev_priv, GEN7_ERR_INT); in ivb_check_fifo_underruns()
248 intel_de_posting_read(dev_priv, SERR_INT); in cpt_check_pch_fifo_underruns()
H A Dintel_pps.c147 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
150 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
153 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
752 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_vdd_on_unlocked()
822 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_vdd_off_sync_unlocked()
949 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_on_unlocked()
957 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_on_unlocked()
965 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_on_unlocked()
1012 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_off_unlocked()
1056 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_backlight_on()
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H A Dintel_pch_refclk.c613 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
632 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
643 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
657 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
H A Dintel_hdmi.c233 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); in g4x_write_infoframe()
304 intel_de_posting_read(dev_priv, reg); in ibx_write_infoframe()
382 intel_de_posting_read(dev_priv, reg); in cpt_write_infoframe()
454 intel_de_posting_read(dev_priv, reg); in vlv_write_infoframe()
531 intel_de_posting_read(dev_priv, ctl_reg); in hsw_write_infoframe()
884 intel_de_posting_read(dev_priv, reg); in g4x_set_infoframes()
904 intel_de_posting_read(dev_priv, reg); in g4x_set_infoframes()
1056 intel_de_posting_read(dev_priv, reg); in ibx_set_infoframes()
1077 intel_de_posting_read(dev_priv, reg); in ibx_set_infoframes()
1113 intel_de_posting_read(dev_priv, reg); in cpt_set_infoframes()
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H A Dintel_pipe_crc.c612 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe)); in intel_crtc_set_crc_source()
647 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe)); in intel_crtc_enable_pipe_crc()
662 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe)); in intel_crtc_disable_pipe_crc()
H A Dintel_dkl_phy.c112 intel_de_posting_read(i915, DKL_REG_MMIO(reg)); in intel_dkl_phy_posting_read()
H A Dintel_vga.c47 intel_de_posting_read(dev_priv, vga_reg); in intel_vga_disable()
H A Dintel_de.h33 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg) in intel_de_posting_read() function
H A Dintel_dpll_mgr.c524 intel_de_posting_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_enable()
533 intel_de_posting_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_enable()
543 intel_de_posting_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_disable()
630 intel_de_posting_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_enable()
638 intel_de_posting_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_enable()
648 intel_de_posting_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
664 intel_de_posting_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_disable()
1276 intel_de_posting_read(dev_priv, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1289 intel_de_posting_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_enable()
1290 intel_de_posting_read(dev_priv, regs[id].cfgcr2); in skl_ddi_pll_enable()
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H A Dintel_dpll.c1607 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1625 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1756 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1786 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); in vlv_enable_pll()
1956 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); in chv_enable_pll()
2011 intel_de_posting_read(dev_priv, DPLL(pipe)); in vlv_disable_pll()
2028 intel_de_posting_read(dev_priv, DPLL(pipe)); in chv_disable_pll()
2054 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_disable_pll()
H A Dintel_backlight.c501 intel_de_posting_read(i915, BLC_PWM_PCH_CTL1); in lpt_enable_backlight()
538 intel_de_posting_read(i915, BLC_PWM_CPU_CTL2); in pch_enable_backlight()
552 intel_de_posting_read(i915, BLC_PWM_PCH_CTL1); in pch_enable_backlight()
582 intel_de_posting_read(i915, BLC_PWM_CTL); in i9xx_enable_backlight()
626 intel_de_posting_read(i915, BLC_PWM_CTL2); in i965_enable_backlight()
659 intel_de_posting_read(i915, VLV_BLC_PWM_CTL2(pipe)); in vlv_enable_backlight()
708 intel_de_posting_read(i915, BXT_BLC_PWM_CTL(panel->backlight.controller)); in bxt_enable_backlight()
739 intel_de_posting_read(i915, BXT_BLC_PWM_CTL(panel->backlight.controller)); in cnp_enable_backlight()
H A Dintel_dvo.c193 intel_de_posting_read(i915, DVO(port)); in intel_disable_dvo()
210 intel_de_posting_read(i915, DVO(port)); in intel_enable_dvo()
H A Dintel_crt.c500 intel_de_posting_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
728 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); in intel_crt_load_detect()
966 intel_de_posting_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
H A Dhsw_ips.c82 intel_de_posting_read(i915, IPS_CTL); in hsw_ips_disable()
H A Dintel_display_power.c1068 intel_de_posting_read(dev_priv, reg); in gen9_dbuf_slice_set()
1263 intel_de_posting_read(dev_priv, D_COMP_BDW); in hsw_write_dcomp()
1297 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
1313 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
1340 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_restore_lcpll()
H A Dintel_lvds.c325 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_enable_lvds()
348 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_disable_lvds()
H A Dintel_gmbus.c288 intel_de_posting_read(i915, bus->gpio_reg); in set_clock()
305 intel_de_posting_read(i915, bus->gpio_reg); in set_data()
H A Dicl_dsi.c364 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
370 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
377 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); in gen11_dsi_program_esc_clk_div()
672 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); in gen11_dsi_map_pll()
H A Dintel_ddi.c1474 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in hsw_set_signal_levels()
2247 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_disable_fec_state()
3187 intel_de_posting_read(dev_priv, reg); in intel_enable_ddi_hdmi()
3439 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in mtl_ddi_prepare_link_retrain()
3453 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in mtl_ddi_prepare_link_retrain()
3481 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_prepare_link_retrain()
3496 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_prepare_link_retrain()
3504 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_prepare_link_retrain()
H A Dvlv_dsi_pll.c547 intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_pll_enable()
H A Dintel_sdvo.c224 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
231 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
248 intel_de_posting_read(dev_priv, GEN3_SDVOB); in intel_sdvo_write_sdvox()
251 intel_de_posting_read(dev_priv, GEN3_SDVOC); in intel_sdvo_write_sdvox()
H A Dintel_display.c440 intel_de_posting_read(dev_priv, reg); in intel_enable_transcoder()
2750 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); in i9xx_set_pipeconf()
3080 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); in ilk_set_pipeconf()
3110 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); in hsw_set_transconf()
7967 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_enable_pipe()
7980 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_enable_pipe()
7985 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); in i830_enable_pipe()
8009 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); in i830_disable_pipe()
8014 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_disable_pipe()

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