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Searched refs:icsr (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/drivers/i2c/
H A Dsh_i2c.c21 ureg(icsr);
72 if (SH_IC_DTE & readb(&dev->icsr)) in sh_irq_dte()
83 if (SH_IC_DTE & readb(&dev->icsr)) in sh_irq_dte_with_tack()
85 if (SH_IC_TACK & readb(&dev->icsr)) in sh_irq_dte_with_tack()
97 if (!(SH_IC_BUSY & readb(&dev->icsr))) in sh_irq_busy()
125 clrbits_8(&dev->icsr, SH_IC_TACK); in sh_i2c_set_addr()
141 writeb(0, &dev->icsr); in sh_i2c_finish()
H A Drcar_iic.c61 u8 icsr; in sh_irq_dte_with_tack() local
65 icsr = readb(priv->base + RCAR_IIC_ICSR); in sh_irq_dte_with_tack()
66 if (RCAR_IC_DTE & icsr) in sh_irq_dte_with_tack()
68 if (RCAR_IC_TACK & icsr) in sh_irq_dte_with_tack()
/openbmc/linux/drivers/irqchip/
H A Dirq-nvic.c42 unsigned long icsr = readl_relaxed(BASEADDR_V7M_SCB + V7M_SCB_ICSR); in nvic_handle_irq() local
43 irq_hw_number_t hwirq = (icsr & V7M_SCB_ICSR_VECTACTIVE) - 16; in nvic_handle_irq()
/openbmc/linux/arch/alpha/include/asm/
H A Dmce.h33 unsigned long icsr; /* CURRENT SETUP OF EV5 IBOX */ member
/openbmc/u-boot/arch/arm/include/asm/
H A Darmv7m.h28 uint32_t icsr; /* Interrupt Control and State Register */ member
/openbmc/linux/arch/alpha/kernel/
H A Dcore_mcpcia.c473 frame->icsr); in mcpcia_print_uncorrectable()