1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 212d8a729Srev13@wp.pl /* 312d8a729Srev13@wp.pl * (C) Copyright 2010,2011 412d8a729Srev13@wp.pl * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com 512d8a729Srev13@wp.pl * 612d8a729Srev13@wp.pl * (C) Copyright 2015 75be93569SKamil Lulko * Kamil Lulko, <kamil.lulko@gmail.com> 812d8a729Srev13@wp.pl */ 912d8a729Srev13@wp.pl 1012d8a729Srev13@wp.pl #ifndef ARMV7M_H 1112d8a729Srev13@wp.pl #define ARMV7M_H 1212d8a729Srev13@wp.pl 13bf4d0495SVikas Manocha /* armv7m fixed base addresses */ 14bf4d0495SVikas Manocha #define V7M_SCS_BASE 0xE000E000 15bf4d0495SVikas Manocha #define V7M_NVIC_BASE (V7M_SCS_BASE + 0x0100) 16bf4d0495SVikas Manocha #define V7M_SCB_BASE (V7M_SCS_BASE + 0x0D00) 17bf4d0495SVikas Manocha #define V7M_PROC_FTR_BASE (V7M_SCS_BASE + 0x0D78) 18bf4d0495SVikas Manocha #define V7M_MPU_BASE (V7M_SCS_BASE + 0x0D90) 19bf4d0495SVikas Manocha #define V7M_FPU_BASE (V7M_SCS_BASE + 0x0F30) 20bf4d0495SVikas Manocha #define V7M_CACHE_MAINT_BASE (V7M_SCS_BASE + 0x0F50) 21bf4d0495SVikas Manocha #define V7M_ACCESS_CNTL_BASE (V7M_SCS_BASE + 0x0F90) 2212d8a729Srev13@wp.pl 2312d8a729Srev13@wp.pl #define V7M_SCB_VTOR 0x08 2412d8a729Srev13@wp.pl 2512d8a729Srev13@wp.pl #if !defined(__ASSEMBLY__) 2612d8a729Srev13@wp.pl struct v7m_scb { 2712d8a729Srev13@wp.pl uint32_t cpuid; /* CPUID Base Register */ 2812d8a729Srev13@wp.pl uint32_t icsr; /* Interrupt Control and State Register */ 2912d8a729Srev13@wp.pl uint32_t vtor; /* Vector Table Offset Register */ 3012d8a729Srev13@wp.pl uint32_t aircr; /* App Interrupt and Reset Control Register */ 31bf4d0495SVikas Manocha uint32_t scr; /* offset 0x10: System Control Register */ 32bf4d0495SVikas Manocha uint32_t ccr; /* offset 0x14: Config and Control Register */ 33bf4d0495SVikas Manocha uint32_t shpr1; /* offset 0x18: System Handler Priority Reg 1 */ 34bf4d0495SVikas Manocha uint32_t shpr2; /* offset 0x1c: System Handler Priority Reg 2 */ 35bf4d0495SVikas Manocha uint32_t shpr3; /* offset 0x20: System Handler Priority Reg 3 */ 36bf4d0495SVikas Manocha uint32_t shcrs; /* offset 0x24: System Handler Control State */ 37bf4d0495SVikas Manocha uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */ 38bf4d0495SVikas Manocha uint32_t hfsr; /* offset 0x2C: HardFault Status Register */ 39bf4d0495SVikas Manocha uint32_t res; /* offset 0x30: reserved */ 40bf4d0495SVikas Manocha uint32_t mmar; /* offset 0x34: MemManage Fault Address Reg */ 41bf4d0495SVikas Manocha uint32_t bfar; /* offset 0x38: BusFault Address Reg */ 42bf4d0495SVikas Manocha uint32_t afsr; /* offset 0x3C: Auxiliary Fault Status Reg */ 4312d8a729Srev13@wp.pl }; 4412d8a729Srev13@wp.pl #define V7M_SCB ((struct v7m_scb *)V7M_SCB_BASE) 4512d8a729Srev13@wp.pl 4612d8a729Srev13@wp.pl #define V7M_AIRCR_VECTKEY 0x5fa 4712d8a729Srev13@wp.pl #define V7M_AIRCR_VECTKEY_SHIFT 16 4812d8a729Srev13@wp.pl #define V7M_AIRCR_ENDIAN (1 << 15) 4912d8a729Srev13@wp.pl #define V7M_AIRCR_PRIGROUP_SHIFT 8 5012d8a729Srev13@wp.pl #define V7M_AIRCR_PRIGROUP_MSK (0x7 << V7M_AIRCR_PRIGROUP_SHIFT) 5112d8a729Srev13@wp.pl #define V7M_AIRCR_SYSRESET (1 << 2) 5212d8a729Srev13@wp.pl 5312d8a729Srev13@wp.pl #define V7M_ICSR_VECTACT_MSK 0xFF 5412d8a729Srev13@wp.pl 55bf4d0495SVikas Manocha #define V7M_CCR_DCACHE 16 56bf4d0495SVikas Manocha #define V7M_CCR_ICACHE 17 57bf4d0495SVikas Manocha 5812d8a729Srev13@wp.pl struct v7m_mpu { 5912d8a729Srev13@wp.pl uint32_t type; /* Type Register */ 6012d8a729Srev13@wp.pl uint32_t ctrl; /* Control Register */ 6112d8a729Srev13@wp.pl uint32_t rnr; /* Region Number Register */ 6212d8a729Srev13@wp.pl uint32_t rbar; /* Region Base Address Register */ 6312d8a729Srev13@wp.pl uint32_t rasr; /* Region Attribute and Size Register */ 6412d8a729Srev13@wp.pl }; 6512d8a729Srev13@wp.pl #define V7M_MPU ((struct v7m_mpu *)V7M_MPU_BASE) 6612d8a729Srev13@wp.pl 6712d8a729Srev13@wp.pl #endif /* !defined(__ASSEMBLY__) */ 6812d8a729Srev13@wp.pl #endif /* ARMV7M_H */ 69