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Searched refs:i915_ggtt_offset (Results 1 – 25 of 41) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_lrc.c878 const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); in init_wa_bb_regs()
887 i915_ggtt_offset(wa_ctx->vma) + in init_wa_bb_regs()
1044 return i915_ggtt_offset(ce->state) + context_wa_bb_offset(ce); in lrc_indirect_bb()
1262 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_timestamp_wa()
1290 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_restore_scratch()
1306 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_cmd_buf_wa()
1442 return i915_ggtt_offset(ce->state) | desc; in lrc_descriptor()
1455 regs[CTX_RING_START] = i915_ggtt_offset(ring->vma); in lrc_update_regs()
1498 if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) { in lrc_check_regs()
1502 i915_ggtt_offset(ring->vma)); in lrc_check_regs()
[all …]
H A Dselftest_lrc.c81 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
445 *cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32); in __live_lrc_state()
448 expected[RING_START_IDX] = i915_ggtt_offset(ce->ring->vma); in __live_lrc_state()
452 *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32); in __live_lrc_state()
567 i915_ggtt_offset(ce->engine->status_page.vma) + in __gpr_read()
598 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in __gpr_read()
740 i915_ggtt_offset(ce->engine->status_page.vma) + in create_timestamp()
1108 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in record_registers()
1241 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in poison_registers()
1588 *cs++ = i915_ggtt_offset(ce->state) + in emit_indirect_ctx_bb_canary()
H A Dintel_context_sseu.c27 offset = i915_ggtt_offset(ce->state) + in gen8_emit_rpcs_config()
H A Dintel_timeline.c209 i915_ggtt_offset(tl->hwsp_ggtt) + in intel_timeline_pin()
317 tl->hwsp_offset = i915_ggtt_offset(tl->hwsp_ggtt) + next_ofs; in __intel_timeline_get_seqno()
354 *hwsp = i915_ggtt_offset(tl->hwsp_ggtt) + in intel_timeline_read_hwsp()
H A Dselftest_mocs.c235 offset = i915_ggtt_offset(vma); in check_mocs_engine()
240 offset -= i915_ggtt_offset(vma); in check_mocs_engine()
H A Dintel_ring_submission.c139 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page()
223 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
271 i915_ggtt_offset(ring->vma)); in xcs_resume()
758 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | in mi_set_context()
765 *cs++ = i915_ggtt_offset(ce->state) | flags; in mi_set_context()
H A Dintel_gt.h115 return i915_ggtt_offset(gt->scratch) + field; in intel_gt_scratch_offset()
H A Dintel_renderstate.c89 so->batch_offset = i915_ggtt_offset(so->vma); in render_state_setup()
H A Dselftest_timeline.c854 w->addr = i915_ggtt_offset(vma); in setup_watcher()
889 w->addr = i915_ggtt_offset(w->vma); in create_watcher()
903 GEM_BUG_ON(w->addr - i915_ggtt_offset(w->vma) > w->vma->size); in check_watcher()
916 end = (w->addr - i915_ggtt_offset(w->vma)) / sizeof(*w->map); in check_watcher()
H A Dgen8_engine_cs.c420 return (i915_ggtt_offset(engine->status_page.vma) + in preempt_address()
748 return i915_ggtt_offset(rq->context->state) + in ccs_semaphore_offset()
H A Dselftest_execlists.c835 *cs++ = i915_ggtt_offset(vma) + 4 * idx; in emit_semaphore_chain()
840 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in emit_semaphore_chain()
909 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in release_queue()
1054 i915_ggtt_offset(ce->engine->status_page.vma) + in create_rewinder()
1620 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
1631 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
1670 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
3229 *cs++ = i915_ggtt_offset(global); in preempt_user()
4246 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in preserved_virtual_engine()
H A Dselftest_engine_pm.c78 u32 offset = i915_ggtt_offset(engine->status_page.vma); in __measure_timestamps()
/openbmc/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_coherency.c226 *cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set()
227 *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set()
232 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
236 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
/openbmc/linux/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c245 i915_ggtt_offset(stream->noa_wait), 0, in live_noa_delay()
352 i915_ggtt_offset(stream->noa_wait), 0, in live_noa_gpr()
378 *cs++ = i915_ggtt_offset(rq->engine->status_page.vma) + in live_noa_gpr()
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dsb.c250 i915_ggtt_offset(dsb->vma)); in intel_dsb_commit()
252 i915_ggtt_offset(dsb->vma) + tail); in intel_dsb_commit()
H A Dintel_overlay.c848 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y); in intel_overlay_do_put_image()
865 iowrite32(i915_ggtt_offset(vma) + params->offset_U, in intel_overlay_do_put_image()
867 iowrite32(i915_ggtt_offset(vma) + params->offset_V, in intel_overlay_do_put_image()
1371 overlay->flip_addr = i915_ggtt_offset(vma); in get_registers()
H A Dintel_fbdev.c297 (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma)); in intelfb_create()
335 i915_ggtt_offset(vma)); in intelfb_create()
/openbmc/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_gsc_fw.c220 u32 offset = i915_ggtt_offset(gsc->local); in emit_gsc_fw_load()
361 offset = i915_ggtt_offset(vma); in gsc_fw_query_compatibility_version()
H A Dintel_huc_fw.c42 pkt_offset = i915_ggtt_offset(huc->heci_pkt); in intel_huc_fw_auth_via_gsccs()
H A Dintel_guc.h374 u32 offset = i915_ggtt_offset(vma); in intel_guc_ggtt_offset()
H A Dintel_gsc_proxy.c127 u64 addr_in = i915_ggtt_offset(gsc->proxy.vma); in proxy_send_to_gsc()
H A Dintel_guc_submission.c2625 desc->process_desc = i915_ggtt_offset(ce->state) + in prepare_context_registration_info_v69()
2627 desc->wq_addr = i915_ggtt_offset(ce->state) + in prepare_context_registration_info_v69()
2698 wq_desc_offset = i915_ggtt_offset(ce->state) + in prepare_context_registration_info_v70()
2700 wq_base_offset = i915_ggtt_offset(ce->state) + in prepare_context_registration_info_v70()
2799 if (i915_ggtt_offset(ce->state) != in __guc_context_pin()
4140 i915_ggtt_offset(engine->status_page.vma)); in setup_hwsp()
5185 return i915_ggtt_offset(ce->state) + in get_children_go_addr()
5195 return i915_ggtt_offset(ce->state) + in get_children_join_addr()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_perf.c543 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in oa_buffer_check_unlocked()
738 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_append_oa_reports()
1056 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_append_oa_reports()
1406 i915_ggtt_offset(scratch)); in gen12_guc_sw_ctx_id()
1578 stream->specific_ctx_id = i915_ggtt_offset(ce->state); in oa_get_render_ctx_id()
1732 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_init_oa_buffer()
1777 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_init_oa_buffer()
2106 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4; in alloc_noa_wait()
2149 *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4; in alloc_noa_wait()
2274 *cs++ = i915_ggtt_offset(stream->noa_wait); in alloc_oa_config_buffer()
[all …]
H A Di915_vma.h173 static inline u32 i915_ggtt_offset(const struct i915_vma *vma) in i915_ggtt_offset() function
/openbmc/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_tiling.c175 if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment)) in i915_vma_fence_prepare()

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