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Searched refs:hw_ctl (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder_phys_wb.c194 (phys_enc->hw_ctl && in dpu_encoder_phys_wb_setup_cdp()
217 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_cdp()
218 } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) { in dpu_encoder_phys_wb_setup_cdp()
225 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_cdp()
298 hw_ctl = phys_enc->hw_ctl; in _dpu_encoder_phys_wb_update_flush()
302 if (!hw_ctl) { in _dpu_encoder_phys_wb_update_flush()
308 hw_ctl->ops.update_pending_flush_wb(hw_ctl, hw_wb->idx); in _dpu_encoder_phys_wb_update_flush()
311 hw_ctl->ops.update_pending_flush_merge_3d(hw_ctl, in _dpu_encoder_phys_wb_update_flush()
315 pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl); in _dpu_encoder_phys_wb_update_flush()
522 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; in dpu_encoder_phys_wb_disable() local
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H A Ddpu_encoder_phys_vid.c289 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_vid_setup_timing_engine()
308 struct dpu_hw_ctl *hw_ctl; in dpu_encoder_phys_vid_vblank_irq() local
312 hw_ctl = phys_enc->hw_ctl; in dpu_encoder_phys_vid_vblank_irq()
326 if (hw_ctl->ops.get_flush_register) in dpu_encoder_phys_vid_vblank_irq()
327 flush_register = hw_ctl->ops.get_flush_register(hw_ctl); in dpu_encoder_phys_vid_vblank_irq()
329 if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl))) in dpu_encoder_phys_vid_vblank_irq()
410 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_vid_enable()
476 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; in dpu_encoder_phys_vid_wait_for_commit_done() local
479 if (!hw_ctl) in dpu_encoder_phys_vid_wait_for_commit_done()
483 (hw_ctl->ops.get_flush_register(hw_ctl) == 0), in dpu_encoder_phys_vid_wait_for_commit_done()
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H A Ddpu_encoder.c1089 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); in dpu_encoder_virt_atomic_mode_set()
1132 phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL; in dpu_encoder_virt_atomic_mode_set()
1133 if (!phys->hw_ctl) { in dpu_encoder_virt_atomic_mode_set()
1498 ctl = phys->hw_ctl; in _dpu_encoder_trigger_flush()
1546 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_trigger_start()
1586 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_hw_reset()
1631 ctl = phys->hw_ctl; in _dpu_encoder_kickoff_phys()
1679 ctl = phys->hw_ctl; in dpu_encoder_trigger_kickoff_pending()
1985 phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl); in dpu_encoder_helper_reset_mixers()
2047 phys_enc->hw_ctl->ops.reset(ctl); in dpu_encoder_helper_phys_cleanup()
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H A Ddpu_encoder_phys_cmd.c57 ctl = phys_enc->hw_ctl; in _dpu_encoder_phys_cmd_update_intf_cfg()
156 phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; in dpu_encoder_phys_cmd_atomic_mode_set()
201 phys_enc->hw_ctl->idx - CTL_0, in _dpu_encoder_phys_cmd_handle_ppdone_timeout()
417 if (!phys_enc->hw_pp || !phys_enc->hw_ctl->ops.setup_intf_cfg) { in _dpu_encoder_phys_cmd_pingpong_config()
454 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_cmd_enable_helper()
562 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_cmd_disable()
678 if (phys_enc->hw_ctl->ops.is_started(phys_enc->hw_ctl)) in dpu_encoder_phys_cmd_wait_for_commit_done()
H A Ddpu_encoder_phys.h179 struct dpu_hw_ctl *hw_ctl; member