1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
7
8 #include <linux/debugfs.h>
9
10 #include <drm/drm_framebuffer.h>
11
12 #include "dpu_encoder_phys.h"
13 #include "dpu_formats.h"
14 #include "dpu_hw_top.h"
15 #include "dpu_hw_wb.h"
16 #include "dpu_hw_lm.h"
17 #include "dpu_hw_merge3d.h"
18 #include "dpu_hw_interrupts.h"
19 #include "dpu_core_irq.h"
20 #include "dpu_vbif.h"
21 #include "dpu_crtc.h"
22 #include "disp/msm_disp_snapshot.h"
23
24 #define to_dpu_encoder_phys_wb(x) \
25 container_of(x, struct dpu_encoder_phys_wb, base)
26
27 /**
28 * dpu_encoder_phys_wb_is_master - report wb always as master encoder
29 * @phys_enc: Pointer to physical encoder
30 */
dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys * phys_enc)31 static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)
32 {
33 /* there is only one physical enc for dpu_writeback */
34 return true;
35 }
36
37 /**
38 * dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
39 * @phys_enc: Pointer to physical encoder
40 */
dpu_encoder_phys_wb_set_ot_limit(struct dpu_encoder_phys * phys_enc)41 static void dpu_encoder_phys_wb_set_ot_limit(
42 struct dpu_encoder_phys *phys_enc)
43 {
44 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
45 struct dpu_vbif_set_ot_params ot_params;
46
47 memset(&ot_params, 0, sizeof(ot_params));
48 ot_params.xin_id = hw_wb->caps->xin_id;
49 ot_params.num = hw_wb->idx - WB_0;
50 ot_params.width = phys_enc->cached_mode.hdisplay;
51 ot_params.height = phys_enc->cached_mode.vdisplay;
52 ot_params.is_wfd = true;
53 ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
54 ot_params.vbif_idx = hw_wb->caps->vbif_idx;
55 ot_params.clk_ctrl = hw_wb->caps->clk_ctrl;
56 ot_params.rd = false;
57
58 dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params);
59 }
60
61 /**
62 * dpu_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
63 * @phys_enc: Pointer to physical encoder
64 */
dpu_encoder_phys_wb_set_qos_remap(struct dpu_encoder_phys * phys_enc)65 static void dpu_encoder_phys_wb_set_qos_remap(
66 struct dpu_encoder_phys *phys_enc)
67 {
68 struct dpu_hw_wb *hw_wb;
69 struct dpu_vbif_set_qos_params qos_params;
70
71 if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
72 DPU_ERROR("invalid arguments\n");
73 return;
74 }
75
76 if (!phys_enc->hw_wb || !phys_enc->hw_wb->caps) {
77 DPU_ERROR("invalid writeback hardware\n");
78 return;
79 }
80
81 hw_wb = phys_enc->hw_wb;
82
83 memset(&qos_params, 0, sizeof(qos_params));
84 qos_params.vbif_idx = hw_wb->caps->vbif_idx;
85 qos_params.xin_id = hw_wb->caps->xin_id;
86 qos_params.clk_ctrl = hw_wb->caps->clk_ctrl;
87 qos_params.num = hw_wb->idx - WB_0;
88 qos_params.is_rt = false;
89
90 DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n",
91 qos_params.num,
92 qos_params.vbif_idx,
93 qos_params.xin_id, qos_params.is_rt);
94
95 dpu_vbif_set_qos_remap(phys_enc->dpu_kms, &qos_params);
96 }
97
98 /**
99 * dpu_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback
100 * @phys_enc: Pointer to physical encoder
101 */
dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys * phys_enc)102 static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc)
103 {
104 struct dpu_hw_wb *hw_wb;
105 struct dpu_hw_qos_cfg qos_cfg;
106 const struct dpu_mdss_cfg *catalog;
107 const struct dpu_qos_lut_tbl *qos_lut_tb;
108
109 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
110 DPU_ERROR("invalid parameter(s)\n");
111 return;
112 }
113
114 catalog = phys_enc->dpu_kms->catalog;
115
116 hw_wb = phys_enc->hw_wb;
117
118 memset(&qos_cfg, 0, sizeof(struct dpu_hw_qos_cfg));
119 qos_cfg.danger_safe_en = true;
120 qos_cfg.danger_lut =
121 catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
122
123 qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
124
125 qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
126 qos_cfg.creq_lut = _dpu_hw_get_qos_lut(qos_lut_tb, 0);
127
128 if (hw_wb->ops.setup_qos_lut)
129 hw_wb->ops.setup_qos_lut(hw_wb, &qos_cfg);
130 }
131
132 /**
133 * dpu_encoder_phys_wb_setup_fb - setup output framebuffer
134 * @phys_enc: Pointer to physical encoder
135 * @fb: Pointer to output framebuffer
136 */
dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys * phys_enc,struct drm_framebuffer * fb)137 static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
138 struct drm_framebuffer *fb)
139 {
140 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
141 struct dpu_hw_wb *hw_wb;
142 struct dpu_hw_wb_cfg *wb_cfg;
143
144 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
145 DPU_ERROR("invalid encoder\n");
146 return;
147 }
148
149 hw_wb = phys_enc->hw_wb;
150 wb_cfg = &wb_enc->wb_cfg;
151
152 wb_cfg->intf_mode = phys_enc->intf_mode;
153 wb_cfg->roi.x1 = 0;
154 wb_cfg->roi.x2 = phys_enc->cached_mode.hdisplay;
155 wb_cfg->roi.y1 = 0;
156 wb_cfg->roi.y2 = phys_enc->cached_mode.vdisplay;
157
158 if (hw_wb->ops.setup_roi)
159 hw_wb->ops.setup_roi(hw_wb, wb_cfg);
160
161 if (hw_wb->ops.setup_outformat)
162 hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
163
164 if (hw_wb->ops.setup_cdp) {
165 const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf;
166
167 hw_wb->ops.setup_cdp(hw_wb, wb_cfg->dest.format,
168 perf->cdp_cfg[DPU_PERF_CDP_USAGE_NRT].wr_enable);
169 }
170
171 if (hw_wb->ops.setup_outaddress)
172 hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
173 }
174
175 /**
176 * dpu_encoder_phys_wb_setup_cdp - setup chroma down prefetch block
177 * @phys_enc:Pointer to physical encoder
178 */
dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys * phys_enc)179 static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc)
180 {
181 struct dpu_hw_wb *hw_wb;
182 struct dpu_hw_ctl *ctl;
183
184 if (!phys_enc) {
185 DPU_ERROR("invalid encoder\n");
186 return;
187 }
188
189 hw_wb = phys_enc->hw_wb;
190 ctl = phys_enc->hw_ctl;
191
192 if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) &&
193 (phys_enc->hw_ctl &&
194 phys_enc->hw_ctl->ops.setup_intf_cfg)) {
195 struct dpu_hw_intf_cfg intf_cfg = {0};
196 struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp;
197 enum dpu_3d_blend_mode mode_3d;
198
199 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
200
201 intf_cfg.intf = DPU_NONE;
202 intf_cfg.wb = hw_wb->idx;
203
204 if (mode_3d && hw_pp && hw_pp->merge_3d)
205 intf_cfg.merge_3d = hw_pp->merge_3d->idx;
206
207 if (phys_enc->hw_pp->merge_3d && phys_enc->hw_pp->merge_3d->ops.setup_3d_mode)
208 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
209 mode_3d);
210
211 /* setup which pp blk will connect to this wb */
212 if (hw_pp && phys_enc->hw_wb->ops.bind_pingpong_blk)
213 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb,
214 phys_enc->hw_pp->idx);
215
216 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
217 } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {
218 struct dpu_hw_intf_cfg intf_cfg = {0};
219
220 intf_cfg.intf = DPU_NONE;
221 intf_cfg.wb = hw_wb->idx;
222 intf_cfg.mode_3d =
223 dpu_encoder_helper_get_3d_blend_mode(phys_enc);
224 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
225 }
226 }
227
228 /**
229 * dpu_encoder_phys_wb_atomic_check - verify and fixup given atomic states
230 * @phys_enc: Pointer to physical encoder
231 * @crtc_state: Pointer to CRTC atomic state
232 * @conn_state: Pointer to connector atomic state
233 */
dpu_encoder_phys_wb_atomic_check(struct dpu_encoder_phys * phys_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)234 static int dpu_encoder_phys_wb_atomic_check(
235 struct dpu_encoder_phys *phys_enc,
236 struct drm_crtc_state *crtc_state,
237 struct drm_connector_state *conn_state)
238 {
239 struct drm_framebuffer *fb;
240 const struct drm_display_mode *mode = &crtc_state->mode;
241
242 DPU_DEBUG("[atomic_check:%d, \"%s\",%d,%d]\n",
243 phys_enc->hw_wb->idx, mode->name, mode->hdisplay, mode->vdisplay);
244
245 if (!conn_state || !conn_state->connector) {
246 DPU_ERROR("invalid connector state\n");
247 return -EINVAL;
248 } else if (conn_state->connector->status !=
249 connector_status_connected) {
250 DPU_ERROR("connector not connected %d\n",
251 conn_state->connector->status);
252 return -EINVAL;
253 }
254
255 if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
256 return 0;
257
258 fb = conn_state->writeback_job->fb;
259
260 DPU_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
261 fb->width, fb->height);
262
263 if (fb->width != mode->hdisplay) {
264 DPU_ERROR("invalid fb w=%d, mode w=%d\n", fb->width,
265 mode->hdisplay);
266 return -EINVAL;
267 } else if (fb->height != mode->vdisplay) {
268 DPU_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
269 mode->vdisplay);
270 return -EINVAL;
271 } else if (fb->width > phys_enc->hw_wb->caps->maxlinewidth) {
272 DPU_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
273 fb->width, phys_enc->hw_wb->caps->maxlinewidth);
274 return -EINVAL;
275 }
276
277 return 0;
278 }
279
280
281 /**
282 * _dpu_encoder_phys_wb_update_flush - flush hardware update
283 * @phys_enc: Pointer to physical encoder
284 */
_dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys * phys_enc)285 static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)
286 {
287 struct dpu_hw_wb *hw_wb;
288 struct dpu_hw_ctl *hw_ctl;
289 struct dpu_hw_pingpong *hw_pp;
290 u32 pending_flush = 0;
291
292 if (!phys_enc)
293 return;
294
295 hw_wb = phys_enc->hw_wb;
296 hw_pp = phys_enc->hw_pp;
297 hw_ctl = phys_enc->hw_ctl;
298
299 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
300
301 if (!hw_ctl) {
302 DPU_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
303 return;
304 }
305
306 if (hw_ctl->ops.update_pending_flush_wb)
307 hw_ctl->ops.update_pending_flush_wb(hw_ctl, hw_wb->idx);
308
309 if (hw_ctl->ops.update_pending_flush_merge_3d && hw_pp && hw_pp->merge_3d)
310 hw_ctl->ops.update_pending_flush_merge_3d(hw_ctl,
311 hw_pp->merge_3d->idx);
312
313 if (hw_ctl->ops.get_pending_flush)
314 pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl);
315
316 DPU_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",
317 hw_ctl->idx - CTL_0, pending_flush,
318 hw_wb->idx - WB_0);
319 }
320
321 /**
322 * dpu_encoder_phys_wb_setup - setup writeback encoder
323 * @phys_enc: Pointer to physical encoder
324 */
dpu_encoder_phys_wb_setup(struct dpu_encoder_phys * phys_enc)325 static void dpu_encoder_phys_wb_setup(
326 struct dpu_encoder_phys *phys_enc)
327 {
328 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
329 struct drm_display_mode mode = phys_enc->cached_mode;
330 struct drm_framebuffer *fb = NULL;
331
332 DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
333 hw_wb->idx - WB_0, mode.name,
334 mode.hdisplay, mode.vdisplay);
335
336 dpu_encoder_phys_wb_set_ot_limit(phys_enc);
337
338 dpu_encoder_phys_wb_set_qos_remap(phys_enc);
339
340 dpu_encoder_phys_wb_set_qos(phys_enc);
341
342 dpu_encoder_phys_wb_setup_fb(phys_enc, fb);
343
344 dpu_encoder_phys_wb_setup_cdp(phys_enc);
345
346 }
347
348 /**
349 * dpu_encoder_phys_wb_done_irq - writeback interrupt handler
350 * @arg: Pointer to writeback encoder
351 */
dpu_encoder_phys_wb_done_irq(void * arg)352 static void dpu_encoder_phys_wb_done_irq(void *arg)
353 {
354 struct dpu_encoder_phys *phys_enc = arg;
355 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
356
357 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
358 unsigned long lock_flags;
359 u32 event = DPU_ENCODER_FRAME_EVENT_DONE;
360
361 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
362
363 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, event);
364
365 dpu_encoder_vblank_callback(phys_enc->parent, phys_enc);
366
367 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
368 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
369 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
370
371 if (wb_enc->wb_conn)
372 drm_writeback_signal_completion(wb_enc->wb_conn, 0);
373
374 /* Signal any waiting atomic commit thread */
375 wake_up_all(&phys_enc->pending_kickoff_wq);
376 }
377
378 /**
379 * dpu_encoder_phys_wb_irq_ctrl - irq control of WB
380 * @phys: Pointer to physical encoder
381 * @enable: indicates enable or disable interrupts
382 */
dpu_encoder_phys_wb_irq_ctrl(struct dpu_encoder_phys * phys,bool enable)383 static void dpu_encoder_phys_wb_irq_ctrl(
384 struct dpu_encoder_phys *phys, bool enable)
385 {
386
387 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);
388
389 if (enable && atomic_inc_return(&wb_enc->wbirq_refcount) == 1)
390 dpu_core_irq_register_callback(phys->dpu_kms,
391 phys->irq[INTR_IDX_WB_DONE], dpu_encoder_phys_wb_done_irq, phys);
392 else if (!enable &&
393 atomic_dec_return(&wb_enc->wbirq_refcount) == 0)
394 dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);
395 }
396
dpu_encoder_phys_wb_atomic_mode_set(struct dpu_encoder_phys * phys_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)397 static void dpu_encoder_phys_wb_atomic_mode_set(
398 struct dpu_encoder_phys *phys_enc,
399 struct drm_crtc_state *crtc_state,
400 struct drm_connector_state *conn_state)
401 {
402
403 phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
404 }
405
_dpu_encoder_phys_wb_handle_wbdone_timeout(struct dpu_encoder_phys * phys_enc)406 static void _dpu_encoder_phys_wb_handle_wbdone_timeout(
407 struct dpu_encoder_phys *phys_enc)
408 {
409 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
410 u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
411
412 wb_enc->wb_done_timeout_cnt++;
413
414 if (wb_enc->wb_done_timeout_cnt == 1)
415 msm_disp_snapshot_state(phys_enc->parent->dev);
416
417 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
418
419 /* request a ctl reset before the next kickoff */
420 phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET;
421
422 if (wb_enc->wb_conn)
423 drm_writeback_signal_completion(wb_enc->wb_conn, 0);
424
425 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, frame_event);
426 }
427
428 /**
429 * dpu_encoder_phys_wb_wait_for_commit_done - wait until request is committed
430 * @phys_enc: Pointer to physical encoder
431 */
dpu_encoder_phys_wb_wait_for_commit_done(struct dpu_encoder_phys * phys_enc)432 static int dpu_encoder_phys_wb_wait_for_commit_done(
433 struct dpu_encoder_phys *phys_enc)
434 {
435 unsigned long ret;
436 struct dpu_encoder_wait_info wait_info;
437 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
438
439 wait_info.wq = &phys_enc->pending_kickoff_wq;
440 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
441 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
442
443 ret = dpu_encoder_helper_wait_for_irq(phys_enc,
444 phys_enc->irq[INTR_IDX_WB_DONE],
445 dpu_encoder_phys_wb_done_irq, &wait_info);
446 if (ret == -ETIMEDOUT)
447 _dpu_encoder_phys_wb_handle_wbdone_timeout(phys_enc);
448 else if (!ret)
449 wb_enc->wb_done_timeout_cnt = 0;
450
451 return ret;
452 }
453
454 /**
455 * dpu_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
456 * @phys_enc: Pointer to physical encoder
457 * Returns: Zero on success
458 */
dpu_encoder_phys_wb_prepare_for_kickoff(struct dpu_encoder_phys * phys_enc)459 static void dpu_encoder_phys_wb_prepare_for_kickoff(
460 struct dpu_encoder_phys *phys_enc)
461 {
462 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
463 struct drm_connector *drm_conn;
464 struct drm_connector_state *state;
465
466 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
467
468 if (!wb_enc->wb_conn || !wb_enc->wb_job) {
469 DPU_ERROR("invalid wb_conn or wb_job\n");
470 return;
471 }
472
473 drm_conn = &wb_enc->wb_conn->base;
474 state = drm_conn->state;
475
476 if (wb_enc->wb_conn && wb_enc->wb_job)
477 drm_writeback_queue_job(wb_enc->wb_conn, state);
478
479 dpu_encoder_phys_wb_setup(phys_enc);
480
481 _dpu_encoder_phys_wb_update_flush(phys_enc);
482 }
483
484 /**
485 * dpu_encoder_phys_wb_needs_single_flush - trigger flush processing
486 * @phys_enc: Pointer to physical encoder
487 */
dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys * phys_enc)488 static bool dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys *phys_enc)
489 {
490 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
491 return false;
492 }
493
494 /**
495 * dpu_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
496 * @phys_enc: Pointer to physical encoder
497 */
dpu_encoder_phys_wb_handle_post_kickoff(struct dpu_encoder_phys * phys_enc)498 static void dpu_encoder_phys_wb_handle_post_kickoff(
499 struct dpu_encoder_phys *phys_enc)
500 {
501 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
502
503 }
504
505 /**
506 * dpu_encoder_phys_wb_enable - enable writeback encoder
507 * @phys_enc: Pointer to physical encoder
508 */
dpu_encoder_phys_wb_enable(struct dpu_encoder_phys * phys_enc)509 static void dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc)
510 {
511 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
512 phys_enc->enable_state = DPU_ENC_ENABLED;
513 }
514 /**
515 * dpu_encoder_phys_wb_disable - disable writeback encoder
516 * @phys_enc: Pointer to physical encoder
517 */
dpu_encoder_phys_wb_disable(struct dpu_encoder_phys * phys_enc)518 static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
519 {
520 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
521 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
522
523 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
524
525 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
526 DPU_ERROR("encoder is already disabled\n");
527 return;
528 }
529
530 /* reset h/w before final flush */
531 if (phys_enc->hw_ctl->ops.clear_pending_flush)
532 phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
533
534 /*
535 * New CTL reset sequence from 5.0 MDP onwards.
536 * If has_3d_merge_reset is not set, legacy reset
537 * sequence is executed.
538 *
539 * Legacy reset sequence has not been implemented yet.
540 * Any target earlier than SM8150 will need it and when
541 * WB support is added to those targets will need to add
542 * the legacy teardown sequence as well.
543 */
544 if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG))
545 dpu_encoder_helper_phys_cleanup(phys_enc);
546
547 phys_enc->enable_state = DPU_ENC_DISABLED;
548 }
549
550 /**
551 * dpu_encoder_phys_wb_destroy - destroy writeback encoder
552 * @phys_enc: Pointer to physical encoder
553 */
dpu_encoder_phys_wb_destroy(struct dpu_encoder_phys * phys_enc)554 static void dpu_encoder_phys_wb_destroy(struct dpu_encoder_phys *phys_enc)
555 {
556 if (!phys_enc)
557 return;
558
559 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
560
561 kfree(phys_enc);
562 }
563
dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys * phys_enc,struct drm_writeback_job * job)564 static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc,
565 struct drm_writeback_job *job)
566 {
567 const struct msm_format *format;
568 struct msm_gem_address_space *aspace;
569 struct dpu_hw_wb_cfg *wb_cfg;
570 int ret;
571 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
572
573 if (!job->fb)
574 return;
575
576 wb_enc->wb_job = job;
577 wb_enc->wb_conn = job->connector;
578 aspace = phys_enc->dpu_kms->base.aspace;
579
580 wb_cfg = &wb_enc->wb_cfg;
581
582 memset(wb_cfg, 0, sizeof(struct dpu_hw_wb_cfg));
583
584 ret = msm_framebuffer_prepare(job->fb, aspace, false);
585 if (ret) {
586 DPU_ERROR("prep fb failed, %d\n", ret);
587 return;
588 }
589
590 format = msm_framebuffer_format(job->fb);
591
592 wb_cfg->dest.format = dpu_get_dpu_format_ext(
593 format->pixel_format, job->fb->modifier);
594 if (!wb_cfg->dest.format) {
595 /* this error should be detected during atomic_check */
596 DPU_ERROR("failed to get format %x\n", format->pixel_format);
597 return;
598 }
599
600 ret = dpu_format_populate_layout(aspace, job->fb, &wb_cfg->dest);
601 if (ret) {
602 DPU_DEBUG("failed to populate layout %d\n", ret);
603 return;
604 }
605
606 wb_cfg->dest.width = job->fb->width;
607 wb_cfg->dest.height = job->fb->height;
608 wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
609
610 if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) &&
611 (wb_cfg->dest.format->element[0] == C1_B_Cb))
612 swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
613
614 DPU_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
615 wb_cfg->dest.plane_addr[0], wb_cfg->dest.plane_addr[1],
616 wb_cfg->dest.plane_addr[2], wb_cfg->dest.plane_addr[3]);
617
618 DPU_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
619 wb_cfg->dest.plane_pitch[0], wb_cfg->dest.plane_pitch[1],
620 wb_cfg->dest.plane_pitch[2], wb_cfg->dest.plane_pitch[3]);
621 }
622
dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys * phys_enc,struct drm_writeback_job * job)623 static void dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys *phys_enc,
624 struct drm_writeback_job *job)
625 {
626 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
627 struct msm_gem_address_space *aspace;
628
629 if (!job->fb)
630 return;
631
632 aspace = phys_enc->dpu_kms->base.aspace;
633
634 msm_framebuffer_cleanup(job->fb, aspace, false);
635 wb_enc->wb_job = NULL;
636 wb_enc->wb_conn = NULL;
637 }
638
dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys * phys_enc)639 static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phys_enc)
640 {
641 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
642
643 if (wb_enc->wb_job)
644 return true;
645 else
646 return false;
647 }
648
649 /**
650 * dpu_encoder_phys_wb_init_ops - initialize writeback operations
651 * @ops: Pointer to encoder operation table
652 */
dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops * ops)653 static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)
654 {
655 ops->is_master = dpu_encoder_phys_wb_is_master;
656 ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set;
657 ops->enable = dpu_encoder_phys_wb_enable;
658 ops->disable = dpu_encoder_phys_wb_disable;
659 ops->destroy = dpu_encoder_phys_wb_destroy;
660 ops->atomic_check = dpu_encoder_phys_wb_atomic_check;
661 ops->wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done;
662 ops->prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff;
663 ops->handle_post_kickoff = dpu_encoder_phys_wb_handle_post_kickoff;
664 ops->needs_single_flush = dpu_encoder_phys_wb_needs_single_flush;
665 ops->trigger_start = dpu_encoder_helper_trigger_start;
666 ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job;
667 ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job;
668 ops->irq_control = dpu_encoder_phys_wb_irq_ctrl;
669 ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit;
670
671 }
672
673 /**
674 * dpu_encoder_phys_wb_init - initialize writeback encoder
675 * @p: Pointer to init info structure with initialization params
676 */
dpu_encoder_phys_wb_init(struct dpu_enc_phys_init_params * p)677 struct dpu_encoder_phys *dpu_encoder_phys_wb_init(
678 struct dpu_enc_phys_init_params *p)
679 {
680 struct dpu_encoder_phys *phys_enc = NULL;
681 struct dpu_encoder_phys_wb *wb_enc = NULL;
682
683 DPU_DEBUG("\n");
684
685 if (!p || !p->parent) {
686 DPU_ERROR("invalid params\n");
687 return ERR_PTR(-EINVAL);
688 }
689
690 wb_enc = kzalloc(sizeof(*wb_enc), GFP_KERNEL);
691 if (!wb_enc) {
692 DPU_ERROR("failed to allocate wb phys_enc enc\n");
693 return ERR_PTR(-ENOMEM);
694 }
695
696 phys_enc = &wb_enc->base;
697
698 dpu_encoder_phys_init(phys_enc, p);
699
700 dpu_encoder_phys_wb_init_ops(&phys_enc->ops);
701 phys_enc->intf_mode = INTF_MODE_WB_LINE;
702
703 atomic_set(&wb_enc->wbirq_refcount, 0);
704
705 wb_enc->wb_done_timeout_cnt = 0;
706
707 DPU_DEBUG("Created dpu_encoder_phys for wb %d\n", phys_enc->hw_wb->idx);
708
709 return phys_enc;
710 }
711