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Searched refs:eth_parents (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7622.c57 static const char * const eth_parents[] = { variable
392 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
438 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
H A Dclk-mt8516.c266 static const char * const eth_parents[] __initconst = { variable
393 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
H A Dclk-mt8167.c387 static const char * const eth_parents[] = { variable
572 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
H A Dclk-mt7629.c86 static const char * const eth_parents[] = { variable
468 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
H A Dclk-mt8365.c347 static const char * const eth_parents[] = { variable
514 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0,
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c172 static const int eth_parents[] = { variable
367 MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c582 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q}; variable
606 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),