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Searched refs:emif_cfg (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/board/ti/ks2_evm/
H A Dddr3_k2hk.c51 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); in ddr3_init()
56 spd_cb.emif_cfg.sdcfg |= 0x1000; in ddr3_init()
57 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); in ddr3_init()
H A Dddr3_k2e.c42 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); in ddr3_init()
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dddr3.c101 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) in ddr3_init_ddremif() argument
103 __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET); in ddr3_init_ddremif()
104 __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET); in ddr3_init_ddremif()
105 __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET); in ddr3_init_ddremif()
106 __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET); in ddr3_init_ddremif()
107 __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET); in ddr3_init_ddremif()
108 __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); in ddr3_init_ddremif()
109 __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); in ddr3_init_ddremif()
H A Dddr3_spd.c369 spd_cb->emif_cfg.sdcfg = spd->sdram_type << 29 | (DDR_TERM & 7) << 25 | in init_ddr3param()
375 spd_cb->emif_cfg.sdcfg |= 1 << 3; in init_ddr3param()
377 spd_cb->emif_cfg.sdtim1 = ((spd->t_wr - 1) & 0x1f) << 25 | in init_ddr3param()
383 spd_cb->emif_cfg.sdtim2 = 0x07 << 10 | ((spd->t_rp - 1) & 0x1f) << 5 | in init_ddr3param()
386 spd_cb->emif_cfg.sdtim3 = ((spd->t_xp - 2) & 0xf) << 28 | in init_ddr3param()
391 spd_cb->emif_cfg.sdtim4 = (spd->t_csta & 0xf) << 28 | in init_ddr3param()
397 spd_cb->emif_cfg.sdrfc = (spd->refresh_rate - 1) & 0xffff; in init_ddr3param()
400 spd_cb->emif_cfg.zqcfg = (spd->rank == 2) ? 0xF0073200 : 0x70073200; in init_ddr3param()
465 dump_emif_config(&spd_cb->emif_cfg); in ddr3_get_dimm_params_from_spd()
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dddr3.h67 struct ddr3_emif_config emif_cfg; member
81 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);