Home
last modified time | relevance | path

Searched refs:emc_dbg (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c661 emc_dbg = emc_readl(emc, EMC_DBG); in tegra210_emc_r21021_set_clock()
693 emc_dbg(emc, STEPS, "Step 1\n"); in tegra210_emc_r21021_set_clock()
825 emc_dbg(emc, STEPS, "Step 2\n"); in tegra210_emc_r21021_set_clock()
841 emc_dbg(emc, STEPS, "Step 3\n"); in tegra210_emc_r21021_set_clock()
861 emc_dbg(emc, STEPS, "Step 4\n"); in tegra210_emc_r21021_set_clock()
872 emc_dbg(emc, STEPS, "Step 5\n"); in tegra210_emc_r21021_set_clock()
889 emc_dbg(emc, STEPS, "Step 6\n"); in tegra210_emc_r21021_set_clock()
895 emc_dbg(emc, STEPS, "Step 7\n"); in tegra210_emc_r21021_set_clock()
1002 emc_dbg(emc, STEPS, "Step 8\n"); in tegra210_emc_r21021_set_clock()
1239 emc_dbg(emc, STEPS, "Step 9\n"); in tegra210_emc_r21021_set_clock()
[all …]
H A Dtegra30-emc.c534 u32 emc_dbg; in emc_prepare_timing_change() local
555 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_prepare_timing_change()
693 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
728 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
1120 u32 fbio_cfg5, emc_cfg, emc_dbg, emc_adr_cfg; in emc_setup_hw() local
1155 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_setup_hw()
1156 emc_dbg |= EMC_DBG_CFG_PRIORITY; in emc_setup_hw()
1157 emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; in emc_setup_hw()
1158 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; in emc_setup_hw()
1159 emc_dbg &= ~EMC_DBG_FORCE_UPDATE; in emc_setup_hw()
[all …]
H A Dtegra20-emc.c598 u32 emc_cfg, emc_dbg, emc_fbio, emc_adr_cfg; in emc_setup_hw() local
627 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_setup_hw()
628 emc_dbg |= EMC_DBG_CFG_PRIORITY; in emc_setup_hw()
629 emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; in emc_setup_hw()
630 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; in emc_setup_hw()
631 emc_dbg &= ~EMC_DBG_FORCE_UPDATE; in emc_setup_hw()
632 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_setup_hw()
H A Dtegra210-emc-core.c886 u32 emc_dbg = emc_readl(emc, EMC_DBG); in tegra210_emc_set_shadow_bypass() local
889 emc_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()
891 emc_writel(emc, emc_dbg & ~EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()
/openbmc/u-boot/arch/arm/include/asm/arch-tegra20/
H A Dsdram_param.h94 u32 emc_dbg; member