36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__)  macro
108 		emc_dbg(emc, EMA_UPDATES, "%s: (s=%lu) EMA: %u\n",	\
498 		emc_dbg(emc, PER_TRAIN, "Periodic training starting\n");  in tegra210_emc_r21021_periodic_compensation()
559 				emc_dbg(emc, EMA_WRITES, "0x%08x <= 0x%08x\n",  in tegra210_emc_r21021_periodic_compensation()
616 	u32 emc_dbg, emc_cfg_pipe_clk, emc_pin;  in tegra210_emc_r21021_set_clock()  local
624 	emc_dbg(emc, INFO, "Running clock change.\n");  in tegra210_emc_r21021_set_clock()
661 	emc_dbg = emc_readl(emc, EMC_DBG);  in tegra210_emc_r21021_set_clock()
675 	emc_dbg(emc, INFO, "Clock change version: %d\n",  in tegra210_emc_r21021_set_clock()
677 	emc_dbg(emc, INFO, "DRAM type = %d\n", dram_type);  in tegra210_emc_r21021_set_clock()
678 	emc_dbg(emc, INFO, "DRAM dev #: %u\n", emc->num_devices);  in tegra210_emc_r21021_set_clock()
679 	emc_dbg(emc, INFO, "Next EMC clksrc: 0x%08x\n", clksrc);  in tegra210_emc_r21021_set_clock()
680 	emc_dbg(emc, INFO, "DLL clksrc:      0x%08x\n", next->dll_clk_src);  in tegra210_emc_r21021_set_clock()
681 	emc_dbg(emc, INFO, "last rate: %u, next rate %u\n", last->rate,  in tegra210_emc_r21021_set_clock()
683 	emc_dbg(emc, INFO, "last period: %u, next period: %u\n",  in tegra210_emc_r21021_set_clock()
685 	emc_dbg(emc, INFO, "  shared_zq_resistor: %d\n", !!shared_zq_resistor);  in tegra210_emc_r21021_set_clock()
686 	emc_dbg(emc, INFO, "  num_channels: %u\n", emc->num_channels);  in tegra210_emc_r21021_set_clock()
687 	emc_dbg(emc, INFO, "  opt_dll_mode: %d\n", opt_dll_mode);  in tegra210_emc_r21021_set_clock()
693 	emc_dbg(emc, STEPS, "Step 1\n");  in tegra210_emc_r21021_set_clock()
694 	emc_dbg(emc, STEPS, "Step 1.1: Disable DLL temporarily.\n");  in tegra210_emc_r21021_set_clock()
706 	emc_dbg(emc, STEPS, "Step 1.2: Disable AUTOCAL temporarily.\n");  in tegra210_emc_r21021_set_clock()
717 	emc_dbg(emc, STEPS, "Step 1.3: Disable other power features.\n");  in tegra210_emc_r21021_set_clock()
825 	emc_dbg(emc, STEPS, "Step 2\n");  in tegra210_emc_r21021_set_clock()
829 		emc_dbg(emc, INFO, "Prelock enabled for target frequency.\n");  in tegra210_emc_r21021_set_clock()
831 		emc_dbg(emc, INFO, "DLL out: 0x%03x\n", value);  in tegra210_emc_r21021_set_clock()
833 		emc_dbg(emc, INFO, "Disabling DLL for target frequency.\n");  in tegra210_emc_r21021_set_clock()
841 	emc_dbg(emc, STEPS, "Step 3\n");  in tegra210_emc_r21021_set_clock()
861 	emc_dbg(emc, STEPS, "Step 4\n");  in tegra210_emc_r21021_set_clock()
872 	emc_dbg(emc, STEPS, "Step 5\n");  in tegra210_emc_r21021_set_clock()
889 	emc_dbg(emc, STEPS, "Step 6\n");  in tegra210_emc_r21021_set_clock()
895 	emc_dbg(emc, STEPS, "Step 7\n");  in tegra210_emc_r21021_set_clock()
896 	emc_dbg(emc, SUB_STEPS, "Step 7.1: Bug 200024907 - Patch RP R2P");  in tegra210_emc_r21021_set_clock()
929 		emc_dbg(emc, INFO, "tRTM = %u, EMC_RP = %u\n", tRTM,  in tegra210_emc_r21021_set_clock()
980 			emc_dbg(emc, INFO, "Skipped WAR\n");  in tegra210_emc_r21021_set_clock()
1002 	emc_dbg(emc, STEPS, "Step 8\n");  in tegra210_emc_r21021_set_clock()
1003 	emc_dbg(emc, SUB_STEPS, "Writing burst_regs\n");  in tegra210_emc_r21021_set_clock()
1082 	emc_dbg(emc, SUB_STEPS, "Writing burst_regs_per_ch\n");  in tegra210_emc_r21021_set_clock()
1108 		emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,  in tegra210_emc_r21021_set_clock()
1116 	emc_dbg(emc, SUB_STEPS, "Writing vref_regs\n");  in tegra210_emc_r21021_set_clock()
1128 		emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,  in tegra210_emc_r21021_set_clock()
1135 	emc_dbg(emc, SUB_STEPS, "Writing trim_regs\n");  in tegra210_emc_r21021_set_clock()
1155 			emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,  in tegra210_emc_r21021_set_clock()
1157 			emc_dbg(emc, EMA_WRITES, "0x%08x <= 0x%08x\n",  in tegra210_emc_r21021_set_clock()
1161 			emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,  in tegra210_emc_r21021_set_clock()
1168 	emc_dbg(emc, SUB_STEPS, "Writing trim_regs_per_ch\n");  in tegra210_emc_r21021_set_clock()
1195 			emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,  in tegra210_emc_r21021_set_clock()
1197 			emc_dbg(emc, EMA_WRITES, "0x%08x <= 0x%08x\n", offset,  in tegra210_emc_r21021_set_clock()
1201 			emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,  in tegra210_emc_r21021_set_clock()
1208 	emc_dbg(emc, SUB_STEPS, "Writing burst_mc_regs\n");  in tegra210_emc_r21021_set_clock()
1214 		emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,  in tegra210_emc_r21021_set_clock()
1223 		emc_dbg(emc, SUB_STEPS, "Writing la_scale_regs\n");  in tegra210_emc_r21021_set_clock()
1226 			emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,  in tegra210_emc_r21021_set_clock()
1239 	emc_dbg(emc, STEPS, "Step 9\n");  in tegra210_emc_r21021_set_clock()
1248 		value = emc_dbg | (EMC_DBG_WRITE_MUX_ACTIVE |  in tegra210_emc_r21021_set_clock()
1253 		emc_writel(emc, emc_dbg, EMC_DBG);  in tegra210_emc_r21021_set_clock()
1260 	emc_dbg(emc, STEPS, "Step 10\n");  in tegra210_emc_r21021_set_clock()
1357 	emc_dbg(emc, STEPS, "Step 11\n");  in tegra210_emc_r21021_set_clock()
1361 	value = emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE | EMC_DBG_WRITE_ACTIVE_ONLY;  in tegra210_emc_r21021_set_clock()
1371 	emc_dbg(emc, STEPS, "Step 12\n");  in tegra210_emc_r21021_set_clock()
1381 	emc_dbg(emc, STEPS, "Step 13\n");  in tegra210_emc_r21021_set_clock()
1384 	ccfifo_writel(emc, emc_dbg, EMC_DBG, 0);  in tegra210_emc_r21021_set_clock()
1390 	emc_dbg(emc, STEPS, "Step 14\n");  in tegra210_emc_r21021_set_clock()
1407 	emc_dbg(emc, STEPS, "Step 15\n");  in tegra210_emc_r21021_set_clock()
1419 	emc_dbg(emc, INFO, "tZQCAL_lpddr4_fc_adj = %u\n", tZQCAL_lpddr4_fc_adj);  in tegra210_emc_r21021_set_clock()
1420 	emc_dbg(emc, INFO, "dst_clk_period = %u\n",  in tegra210_emc_r21021_set_clock()
1422 	emc_dbg(emc, INFO, "next->dram_timings[T_PDEX] = %u\n",  in tegra210_emc_r21021_set_clock()
1424 	emc_dbg(emc, INFO, "zq_latch_dvfs_wait_time = %d\n",  in tegra210_emc_r21021_set_clock()
1496 	emc_dbg(emc, STEPS, "Step 17\n");  in tegra210_emc_r21021_set_clock()
1505 	emc_dbg(emc, STEPS, "Step 18\n");  in tegra210_emc_r21021_set_clock()
1526 	emc_dbg(emc, STEPS, "Step 19\n");  in tegra210_emc_r21021_set_clock()
1586 	emc_dbg(emc, STEPS, "Step 20\n");  in tegra210_emc_r21021_set_clock()
1600 	emc_dbg(emc, STEPS, "Step 21\n");  in tegra210_emc_r21021_set_clock()
1603 		ccfifo_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE,  in tegra210_emc_r21021_set_clock()
1613 		ccfifo_writel(emc, emc_dbg, EMC_DBG, 0);  in tegra210_emc_r21021_set_clock()
1620 	emc_dbg(emc, STEPS, "Step 22\n");  in tegra210_emc_r21021_set_clock()
1640 	emc_dbg(emc, STEPS, "Step 23\n");  in tegra210_emc_r21021_set_clock()
1662 	emc_dbg(emc, STEPS, "Step 25\n");  in tegra210_emc_r21021_set_clock()
1676 	emc_dbg(emc, STEPS, "Step 26\n");  in tegra210_emc_r21021_set_clock()
1705 	emc_dbg(emc, STEPS, "Step 27\n");  in tegra210_emc_r21021_set_clock()
1718 	emc_dbg(emc, STEPS, "Step 28\n");  in tegra210_emc_r21021_set_clock()
1730 	emc_dbg(emc, STEPS, "Step 29\n");  in tegra210_emc_r21021_set_clock()
1751 	emc_dbg(emc, STEPS, "Step 30: Re-enable DLL and AUTOCAL\n");  in tegra210_emc_r21021_set_clock()