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Searched refs:effective_cs (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c53 for (effective_cs = 0; effective_cs < MAX_CS_NUM; effective_cs++) in ddr3_tip_dynamic_read_leveling()
58 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_read_leveling()
265 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_read_leveling()
288 effective_cs = 0; in ddr3_tip_dynamic_read_leveling()
876 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_write_leveling()
1037 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_write_leveling()
1116 effective_cs = 0; in ddr3_tip_dynamic_write_leveling()
1716 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) in mv_ddr_rl_dqs_burst()
1723 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in mv_ddr_rl_dqs_burst()
1732 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in mv_ddr_rl_dqs_burst()
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H A Dddr3_training_pbs.c73 CRX_PHY_REG(effective_cs) : in ddr3_tip_pbs()
74 CTX_PHY_REG(effective_cs); in ddr3_tip_pbs()
188 (0x14 + effective_cs * 0x10); in ddr3_tip_pbs()
358 (0x3 + effective_cs * 4) : in ddr3_tip_pbs()
359 (0x1 + effective_cs * 4); in ddr3_tip_pbs()
592 (0x3 + effective_cs * 4) : in ddr3_tip_pbs()
593 (0x1 + effective_cs * 4); in ddr3_tip_pbs()
824 [effective_cs])); in ddr3_tip_pbs()
831 [effective_cs])); in ddr3_tip_pbs()
854 CRX_PHY_REG(effective_cs) : in ddr3_tip_pbs()
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H A Dddr3_training.c2025 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_ddr3_training_main_flow()
2086 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_ddr3_training_main_flow()
2122 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_ddr3_training_main_flow()
2142 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_ddr3_training_main_flow()
2190 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_ddr3_training_main_flow()
2247 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_ddr3_training_main_flow()
2266 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_ddr3_training_main_flow()
2373 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_ddr3_training_main_flow()
2394 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_ddr3_training_main_flow()
2415 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_ddr3_training_main_flow()
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H A Dddr3_training_centralization.c94 reg_phy_off = CTX_PHY_REG(effective_cs); in ddr3_tip_centralization()
98 reg_phy_off = CRX_PHY_REG(effective_cs); in ddr3_tip_centralization()
189 effective_cs, pattern_id, in ddr3_tip_centralization()
442 effective_cs, &reg); in ddr3_tip_centralization()
456 effective_cs, reg)); in ddr3_tip_centralization()
512 if ((ddr3_tip_special_rx_run_once_flag & (1 << effective_cs)) == (1 << effective_cs)) in ddr3_tip_special_rx()
627 PBS_RX_PHY_REG(effective_cs, pad_num), in ddr3_tip_special_rx()
651 PBS_RX_PHY_REG(effective_cs, 4), in ddr3_tip_special_rx()
658 PBS_RX_PHY_REG(effective_cs, 4), in ddr3_tip_special_rx()
664 PBS_RX_PHY_REG(effective_cs, 5), in ddr3_tip_special_rx()
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H A Dddr3_training_ip_engine.c461 reg_data = PBS_RX_BCAST_PHY_REG(effective_cs); in ddr3_tip_ip_training()
464 reg_data = PBS_TX_BCAST_PHY_REG(effective_cs); in ddr3_tip_ip_training()
475 reg_data = CTX_PHY_REG(effective_cs); in ddr3_tip_ip_training()
479 reg_data = CRX_PHY_REG(effective_cs); in ddr3_tip_ip_training()
890 (effective_cs << 26); in ddr3_tip_load_pattern_to_mem()
1473 CTX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
1480 RL_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
1487 CRX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
1495 CTX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
1502 RL_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
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H A Dddr3_training_leveling.h12 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
H A Dddr3_init.h123 extern u32 effective_cs;