Lines Matching refs:effective_cs
53 for (effective_cs = 0; effective_cs < MAX_CS_NUM; effective_cs++) in ddr3_tip_dynamic_read_leveling()
56 rl_values[effective_cs][bus_num][if_id] = 0; in ddr3_tip_dynamic_read_leveling()
58 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_read_leveling()
94 effective_cs, STRESS_NONE, DURATION_SINGLE)); in ddr3_tip_dynamic_read_leveling()
115 (0x301b01 | effective_cs << 2), 0x3c3fef)); in ddr3_tip_dynamic_read_leveling()
214 if_id, effective_cs, bus_num)); in ddr3_tip_dynamic_read_leveling()
225 rl_values[effective_cs][bus_num] in ddr3_tip_dynamic_read_leveling()
265 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_read_leveling()
274 data = rl_values[effective_cs][bus_num][if_id]; in ddr3_tip_dynamic_read_leveling()
282 RL_PHY_REG(effective_cs), in ddr3_tip_dynamic_read_leveling()
288 effective_cs = 0; in ddr3_tip_dynamic_read_leveling()
690 RL_PHY_REG(effective_cs), in ddr3_tip_dynamic_per_bit_read_leveling()
764 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs, in ddr3_tip_calc_cs_mask() argument
797 *cs_mask = (*cs_mask | (~(1 << effective_cs))) & CS_BIT_MASK; in ddr3_tip_calc_cs_mask()
876 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_write_leveling()
885 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs, in ddr3_tip_dynamic_write_leveling()
897 0x1498, (0x3 << (effective_cs * 2)), 0xf)); in ddr3_tip_dynamic_write_leveling()
944 wl_values[effective_cs][bus_cnt][0] = (u8)data_read[0]; in ddr3_tip_dynamic_write_leveling()
959 reg_data = wl_values[effective_cs][bus_cnt][if_id] + 16; in ddr3_tip_dynamic_write_leveling()
986 wl_values[effective_cs] in ddr3_tip_dynamic_write_leveling()
988 wl_values[effective_cs] in ddr3_tip_dynamic_write_leveling()
993 wl_values[effective_cs] in ddr3_tip_dynamic_write_leveling()
1037 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_write_leveling()
1055 wl_values[effective_cs][bus_cnt] in ddr3_tip_dynamic_write_leveling()
1086 WL_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling()
1116 effective_cs = 0; in ddr3_tip_dynamic_write_leveling()
1192 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1212 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1217 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1238 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1243 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1268 effective_cs, if_id)); in ddr3_tip_dynamic_write_leveling_supp()
1301 DDR_PHY_DATA, WL_PHY_REG(effective_cs), &data)); in ddr3_tip_wl_supp_align_phase_shift()
1313 WL_PHY_REG(effective_cs), write_data); in ddr3_tip_wl_supp_align_phase_shift()
1325 WL_PHY_REG(effective_cs), write_data); in ddr3_tip_wl_supp_align_phase_shift()
1337 WL_PHY_REG(effective_cs), write_data); in ddr3_tip_wl_supp_align_phase_shift()
1349 WL_PHY_REG(effective_cs), write_data); in ddr3_tip_wl_supp_align_phase_shift()
1358 WL_PHY_REG(effective_cs), data); in ddr3_tip_wl_supp_align_phase_shift()
1393 ((SDRAM_CS_SIZE + 1) * effective_cs)), 1, read_pattern)); in ddr3_tip_xsb_compare_test()
1398 effective_cs, if_id, bus_id, in ddr3_tip_xsb_compare_test()
1432 effective_cs, if_id, bus_id, num_of_succ_byte_compare)); in ddr3_tip_xsb_compare_test()
1716 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) in mv_ddr_rl_dqs_burst()
1723 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in mv_ddr_rl_dqs_burst()
1732 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in mv_ddr_rl_dqs_burst()
1736 effective_cs << ODPG_DATA_CS_OFFS, in mv_ddr_rl_dqs_burst()
1738 rl_min_val[effective_cs] = MAX_RL_VALUE; in mv_ddr_rl_dqs_burst()
1739 rl_max_val[effective_cs] = 0; in mv_ddr_rl_dqs_burst()
1749 rd_sample << RD_SMPL_DLY_CS_OFFS(effective_cs), in mv_ddr_rl_dqs_burst()
1750 RD_SMPL_DLY_CS_MASK << RD_SMPL_DLY_CS_OFFS(effective_cs)); in mv_ddr_rl_dqs_burst()
1752 rd_ready << RD_RDY_DLY_CS_OFFS(effective_cs), in mv_ddr_rl_dqs_burst()
1753 RD_RDY_DLY_CS_MASK << RD_RDY_DLY_CS_OFFS(effective_cs)); in mv_ddr_rl_dqs_burst()
1764 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1784 if (rl_state[effective_cs][subphy_id][if_id] == RL_BEHIND) in mv_ddr_rl_dqs_burst()
1792 __func__, effective_cs, i, subphy_id, in mv_ddr_rl_dqs_burst()
1793 rl_state[effective_cs][subphy_id][if_id], in mv_ddr_rl_dqs_burst()
1796 switch (rl_state[effective_cs][subphy_id][if_id]) { in mv_ddr_rl_dqs_burst()
1801 rl_state[effective_cs][subphy_id][if_id] = RL_INSIDE; in mv_ddr_rl_dqs_burst()
1802 rl_values[effective_cs][subphy_id][if_id] = i; in mv_ddr_rl_dqs_burst()
1803 rl_min_values[effective_cs][subphy_id][if_id] = i; in mv_ddr_rl_dqs_burst()
1806 rl_state[effective_cs][subphy_id][if_id])); in mv_ddr_rl_dqs_burst()
1826 rl_max_values[effective_cs][subphy_id][if_id] = i; in mv_ddr_rl_dqs_burst()
1827 if ((rl_max_values[effective_cs][subphy_id][if_id] - in mv_ddr_rl_dqs_burst()
1828 rl_min_values[effective_cs][subphy_id][if_id]) > in mv_ddr_rl_dqs_burst()
1830 rl_state[effective_cs][subphy_id][if_id] = RL_BEHIND; in mv_ddr_rl_dqs_burst()
1831 rl_values[effective_cs][subphy_id][if_id] = in mv_ddr_rl_dqs_burst()
1832 (i + rl_values[effective_cs][subphy_id][if_id]) / 2; in mv_ddr_rl_dqs_burst()
1836 if (rl_min_val[effective_cs] > in mv_ddr_rl_dqs_burst()
1837 rl_values[effective_cs][subphy_id][if_id]) in mv_ddr_rl_dqs_burst()
1838 rl_min_val[effective_cs] = in mv_ddr_rl_dqs_burst()
1839 rl_values[effective_cs][subphy_id][if_id]; in mv_ddr_rl_dqs_burst()
1840 if (rl_max_val[effective_cs] < in mv_ddr_rl_dqs_burst()
1841 rl_values[effective_cs][subphy_id][if_id]) in mv_ddr_rl_dqs_burst()
1842 rl_max_val[effective_cs] = in mv_ddr_rl_dqs_burst()
1843 rl_values[effective_cs][subphy_id][if_id]; in mv_ddr_rl_dqs_burst()
1849 if ((i - rl_values[effective_cs][subphy_id][if_id]) < in mv_ddr_rl_dqs_burst()
1852 rl_state[effective_cs][subphy_id][if_id] = RL_AHEAD; in mv_ddr_rl_dqs_burst()
1855 rl_state[effective_cs][subphy_id][if_id])); in mv_ddr_rl_dqs_burst()
1857 rl_state[effective_cs][subphy_id][if_id] = RL_BEHIND; in mv_ddr_rl_dqs_burst()
1858 rl_values[effective_cs][subphy_id][if_id] = in mv_ddr_rl_dqs_burst()
1859 (i + rl_values[effective_cs][subphy_id][if_id]) / 2; in mv_ddr_rl_dqs_burst()
1862 rl_state[effective_cs][subphy_id][if_id], in mv_ddr_rl_dqs_burst()
1863 rl_values[effective_cs][subphy_id][if_id])); in mv_ddr_rl_dqs_burst()
1867 if (rl_min_val[effective_cs] > in mv_ddr_rl_dqs_burst()
1868 rl_values[effective_cs][subphy_id][if_id]) in mv_ddr_rl_dqs_burst()
1869 rl_min_val[effective_cs] = in mv_ddr_rl_dqs_burst()
1870 rl_values[effective_cs][subphy_id][if_id]; in mv_ddr_rl_dqs_burst()
1871 if (rl_max_val[effective_cs] < in mv_ddr_rl_dqs_burst()
1872 rl_values[effective_cs][subphy_id][if_id]) in mv_ddr_rl_dqs_burst()
1873 rl_max_val[effective_cs] = in mv_ddr_rl_dqs_burst()
1874 rl_values[effective_cs][subphy_id][if_id]; in mv_ddr_rl_dqs_burst()
1893 __func__, effective_cs, pass_lock_num, MAX_BUS_NUM, init_pass_lock_num)); in mv_ddr_rl_dqs_burst()
1899 (rl_state[effective_cs][subphy_id][if_id] == RL_BEHIND) ? in mv_ddr_rl_dqs_burst()
1907 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in mv_ddr_rl_dqs_burst()
1909 i = rl_min_val[effective_cs]; in mv_ddr_rl_dqs_burst()
1913 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1914 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1919 rd_sample << RD_SMPL_DLY_CS_OFFS(effective_cs), in mv_ddr_rl_dqs_burst()
1920 RD_SMPL_DLY_CS_MASK << RD_SMPL_DLY_CS_OFFS(effective_cs)); in mv_ddr_rl_dqs_burst()
1922 rd_ready << RD_RDY_DLY_CS_OFFS(effective_cs), in mv_ddr_rl_dqs_burst()
1923 RD_RDY_DLY_CS_MASK << RD_RDY_DLY_CS_OFFS(effective_cs)); in mv_ddr_rl_dqs_burst()
1926 __func__, effective_cs, min_phase, max_phase, rd_sample)); in mv_ddr_rl_dqs_burst()
1931 i = rl_values[effective_cs][subphy_id][if_id] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE); in mv_ddr_rl_dqs_burst()
1937 __func__, effective_cs, subphy_id, final_rd_sample, in mv_ddr_rl_dqs_burst()
1943 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()