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Searched refs:e500v2 (Results 1 – 17 of 17) sorted by relevance

/openbmc/qemu/target/ppc/
H A Dcpu-models.c295 CPU_POWERPC_e500v2_v10, POWERPC_SVR_E500, e500v2);
297 CPU_POWERPC_e500v2_v20, POWERPC_SVR_E500, e500v2);
299 CPU_POWERPC_e500v2_v21, POWERPC_SVR_E500, e500v2);
301 CPU_POWERPC_e500v2_v22, POWERPC_SVR_E500, e500v2);
303 CPU_POWERPC_e500v2_v30, POWERPC_SVR_E500, e500v2);
314 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2)
316 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2)
318 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2)
320 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2)
336 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2)
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H A Dcpu_init.c3075 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) in POWERPC_FAMILY()
3080 dc->desc = "e500v2 core"; in init_proc_e500v2()
3083 POWERPC_FAMILY(e500v2) POWERPC_FAMILY() argument
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dbsc9132si-pre.dtsi55 cpu0: PowerPC,e500v2@0 {
61 cpu1: PowerPC,e500v2@1 {
H A Dc293si-pre.dtsi57 PowerPC,e500v2@0 {
H A Dbsc9131si-pre.dtsi57 compatible = "fsl,e500v2";
H A De500v2_power_isa.dtsi2 * e500v2 Power ISA Device Tree Source (include)
/openbmc/qemu/docs/system/ppc/
H A Dppce500.rst12 * PowerPC e500 series core (e500v2/e500mc/e5500/e6500)
42 * e500v2
52 it creates a machine with e500v2 core. The following example shows an e6500
147 these SoCs are e500v2 based MPC85xx series, hence you cannot test anything
/openbmc/openbmc/poky/meta/conf/machine/include/powerpc/
H A Dtune-ppce500v2.inc21 QEMU_EXTRAOPTIONS:tune-ppce500v2 = " -cpu e500v2"
/openbmc/linux/Documentation/powerpc/
H A Dcpu_families.rst201 | e500v2 |
/openbmc/linux/arch/powerpc/platforms/85xx/
H A DKconfig24 The BSC9131 is a heterogeneous SoC containing an e500v2 powerpc and a
39 BSC9132 is a heterogeneous SoC containing dual e500v2 powerpc cores
/openbmc/u-boot/board/freescale/c29xpcie/
H A DREADME7 It combines a single e500v2 core with necessary SEC engines.
/openbmc/u-boot/doc/
H A DREADME.mpc85xx4 Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A DREADME4 It combines Power Architecture e500v2 and DSP StarCore SC3850 core
/openbmc/u-boot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PB7 based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
H A DREADME.P1010RDB-PA6 based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A DKconfig1176 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1527 around limitations in e500v1 and e500v2 external debugger
/openbmc/linux/arch/powerpc/platforms/
H A DKconfig.cputype306 e500v1 or e500v2.