Searched refs:drvsel (Results 1 – 5 of 5) sorted by relevance
23 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ argument24 ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))26 #define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \ argument27 ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
34 unsigned int drvsel; member56 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); in socfpga_dwmci_clksel()63 priv->drvsel, priv->smplsel); in socfpga_dwmci_clksel()127 priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), in socfpga_dwmmc_ofdata_to_platdata()
27 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \ argument28 ((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0))
84 drvsel = <3>;
28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct