| /openbmc/linux/drivers/ata/ |
| H A D | ahci_dwc.c | 122 u32 dmacr[AHCI_MAX_PORTS]; member
265 u32 port, dmacr, ts; in ahci_dwc_init_dmacr() local
284 dmacr = readl(port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_init_dmacr()
288 dmacr &= ~AHCI_DWC_PORT_TXTS_MASK; in ahci_dwc_init_dmacr()
289 dmacr |= FIELD_PREP(AHCI_DWC_PORT_TXTS_MASK, ts); in ahci_dwc_init_dmacr()
294 dmacr &= ~AHCI_DWC_PORT_RXTS_MASK; in ahci_dwc_init_dmacr()
295 dmacr |= FIELD_PREP(AHCI_DWC_PORT_RXTS_MASK, ts); in ahci_dwc_init_dmacr()
298 writel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_init_dmacr()
299 dpriv->dmacr[port] = dmacr; in ahci_dwc_init_dmacr()
361 writel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_reinit_host()
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| H A D | sata_dwc_460ex.c | 58 u32 dmacr; /* DMA Control */ member
689 u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr); in sata_dwc_clear_dmacr() local
692 dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr); in sata_dwc_clear_dmacr()
693 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr); in sata_dwc_clear_dmacr()
695 dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr); in sata_dwc_clear_dmacr()
696 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr); in sata_dwc_clear_dmacr()
705 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, in sata_dwc_clear_dmacr()
877 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, in sata_dwc_port_start()
987 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, in sata_dwc_bmdma_start_by_tag()
990 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, in sata_dwc_bmdma_start_by_tag()
[all …]
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| /openbmc/linux/drivers/tty/serial/ |
| H A D | amba-pl011.c | 545 u16 dmacr; in pl011_dma_tx_callback() local
552 dmacr = uap->dmacr; in pl011_dma_tx_callback()
553 uap->dmacr = dmacr & ~UART011_TXDMAE; in pl011_dma_tx_callback()
668 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_refill()
703 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_irq()
744 u16 dmacr; in pl011_dma_tx_start() local
770 dmacr = uap->dmacr; in pl011_dma_tx_start()
771 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_start()
788 uap->dmacr = dmacr; in pl011_dma_tx_start()
854 uap->dmacr |= UART011_RXDMAE; in pl011_dma_rx_trigger_dma()
[all …]
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| /openbmc/u-boot/drivers/spi/ |
| H A D | lpc32xx_ssp.c | 27 u32 dmacr; member
90 writel(0, &lslave->regs->dmacr); /* do not do DMAs */ in spi_setup_slave()
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| H A D | rk_spi.h | 30 u32 dmacr; member
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| H A D | rk_spi.c | 67 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr)); in rkspi_dump_regs()
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| /openbmc/qemu/hw/char/ |
| H A D | pl011.c | 205 r = s->dmacr; in pl011_read()
319 s->dmacr = value; in pl011_write()
442 VMSTATE_UINT32(dmacr, PL011State),
499 s->dmacr = 0; in pl011_reset()
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| /openbmc/linux/Documentation/devicetree/bindings/display/imx/ |
| H A D | fsl,imx-lcdc.yaml | 53 fsl,dmacr:
79 fsl,dmacr: false
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| /openbmc/qemu/include/hw/char/ |
| H A D | pl011.h | 40 uint32_t dmacr; member
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| /openbmc/linux/include/linux/fsl/ |
| H A D | guts.h | 106 u32 dmacr; /* 0x.0908 - DMA Control Register */ member
160 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); in guts_set_dmacr()
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| /openbmc/linux/drivers/dma/xilinx/ |
| H A D | xilinx_dma.c | 2539 u32 dmacr; in xilinx_vdma_channel_set_config() local
2544 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_vdma_channel_set_config()
2553 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN; in xilinx_vdma_channel_set_config()
2555 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN; in xilinx_vdma_channel_set_config()
2556 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK; in xilinx_vdma_channel_set_config()
2557 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; in xilinx_vdma_channel_set_config()
2572 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK; in xilinx_vdma_channel_set_config()
2578 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK; in xilinx_vdma_channel_set_config()
2579 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; in xilinx_vdma_channel_set_config()
2584 dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK; in xilinx_vdma_channel_set_config()
[all …]
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| /openbmc/u-boot/drivers/sound/ |
| H A D | rockchip_i2s.c | 21 u32 dmacr; /* I2S_DMACR, 0x10 */ member
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| /openbmc/linux/drivers/spi/ |
| H A D | spi-pl022.c | 422 u16 dmacr; member
561 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); in restore_state()
1964 chip->dmacr = 0; in pl022_setup()
1970 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1972 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1977 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
1979 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
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| H A D | spi-rockchip.c | 535 u32 dmacr = 0; in rockchip_spi_config() local
580 dmacr |= TF_DMA_EN; in rockchip_spi_config()
582 dmacr |= RF_DMA_EN; in rockchip_spi_config()
600 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); in rockchip_spi_config()
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | imxfb.c | 186 u_int dmacr; member
680 if (fbi->dmacr) in imxfb_activate_var()
681 writel(fbi->dmacr, fbi->regs + LCDC_DMACR); in imxfb_activate_var()
737 of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr); in imxfb_init_fbinfo()
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx27-eukrea-mbimxsd27-baseboard.dts | 91 fsl,dmacr = <0x00040060>;
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| H A D | imx27-apf27dev.dts | 94 fsl,dmacr = <0x00020010>;
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| H A D | imx27-phytec-phycore-rdk.dts | 74 fsl,dmacr = <0x00020010>;
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| H A D | imx25-pdk.dts | 242 fsl,dmacr = <0x00020010>;
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| /openbmc/linux/drivers/dma/ |
| H A D | mpc512x_dma.c | 95 u32 dmacr; /* DMA control register */ member
1023 out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_ERCA); in mpc_dma_probe()
1034 out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG | in mpc_dma_probe()
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| /openbmc/u-boot/drivers/net/ |
| H A D | zynq_gem.c | 134 u32 dmacr; /* 0x10 - DMA Control reg */ member
447 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); in zynq_gem_init()
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| /openbmc/u-boot/drivers/ata/ |
| H A D | dwc_ahsata.c | 42 u32 dmacr; member
482 writel_with_flush(0x00004444, &port_mmio->dmacr); in ahci_port_start()
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| /openbmc/linux/drivers/net/ethernet/intel/i40e/ |
| H A D | i40e_adminq_cmd.h | 427 __le32 dmacr; member
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