| /openbmc/linux/drivers/gpu/drm/i915/soc/ |
| H A D | intel_pch.c | 17 drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5); in intel_pch_type()
22 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
27 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
33 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
40 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
47 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
55 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
63 !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); in intel_pch_type()
114 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in intel_pch_type()
125 drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && in intel_pch_type()
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| H A D | intel_pch.h | 67 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) argument
68 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) argument
69 #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP) argument
70 #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) argument
71 #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) argument
72 #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) argument
73 #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) argument
74 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) argument
75 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) argument
76 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) argument
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| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_display_irq.c | 52 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) { in ilk_update_display_irq()
54 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); in ilk_update_display_irq()
85 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in bdw_update_port_irq()
234 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in i915_enable_pipestat()
257 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in i915_disable_pipestat()
274 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); in i915_has_asle()
386 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()
1044 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in gen8_de_irq_handler()
1409 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u); in vlv_display_irq_postinstall()
1657 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen8_de_irq_postinstall()
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| H A D | intel_fifo_underrun.c | 66 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
84 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
125 intel_de_write(dev_priv, reg, in i9xx_set_fifo_underrun_reporting()
184 drm_err(&dev_priv->drm, in ivb_set_fifo_underrun_reporting()
274 drm_err(&dev_priv->drm, in cpt_set_fifo_underrun_reporting()
293 if (HAS_GMCH(dev_priv)) in __intel_set_cpu_fifo_underrun_reporting()
295 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) in __intel_set_cpu_fifo_underrun_reporting()
372 if (HAS_PCH_IBX(dev_priv)) in intel_set_pch_fifo_underrun_reporting()
405 if (HAS_GMCH(dev_priv) && in intel_cpu_fifo_underrun_irq_handler()
482 if (HAS_GMCH(dev_priv)) in intel_check_cpu_fifo_underruns()
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| H A D | intel_display_power_well.c | 420 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in icl_combo_phy_aux_power_well_enable()
446 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in icl_combo_phy_aux_power_well_disable()
601 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && in hsw_power_well_enabled()
621 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), in assert_can_enable_dc9()
635 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), in assert_can_disable_dc9()
701 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen9_dc_mask()
826 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) in gen9_enable_dc5()
855 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) in skl_enable_dc6()
987 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen9_disable_dc_states()
1167 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), in vlv_init_display_clock_gating()
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| H A D | intel_pch_refclk.c | 33 lpt_fdi_reset_mphy(dev_priv); in lpt_fdi_program_mphy()
111 mutex_lock(&dev_priv->sb_lock); in lpt_disable_iclkip()
183 lpt_disable_iclkip(dev_priv); in lpt_program_iclkip()
194 drm_dbg_kms(&dev_priv->drm, in lpt_program_iclkip()
198 mutex_lock(&dev_priv->sb_lock); in lpt_program_iclkip()
278 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) && in lpt_enable_clkout_dp()
407 if (IS_BROADWELL(dev_priv) && in spll_uses_pch_ssc()
426 if ((IS_BROADWELL(dev_priv) || IS_HASWELL_ULT(dev_priv)) && in wrpll_uses_pch_ssc()
521 if (HAS_PCH_IBX(dev_priv)) { in ilk_init_pch_refclk()
543 drm_dbg_kms(&dev_priv->drm, in ilk_init_pch_refclk()
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| H A D | intel_cdclk.c | 84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
1843 return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) && in pll_enable_wa_needed()
1889 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in _bxt_set_cdclk()
1912 if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) in bxt_set_cdclk()
1948 else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv)) in bxt_set_cdclk()
2031 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in bxt_sanitize_cdclk()
2215 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) in intel_cdclk_can_cd2x_update()
2530 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pixel_rate_to_cdclk()
2648 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { in intel_crtc_compute_min_cdclk()
3170 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_compute_max_dotclk()
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| H A D | intel_fdi.c | 27 if (HAS_DDI(dev_priv)) { in assert_fdi_tx()
139 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
143 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
149 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in ilk_check_fdi_lanes()
151 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
178 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
186 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
293 drm_WARN_ON(&dev_priv->drm, in cpt_set_fdi_bc_bifurcation()
296 drm_WARN_ON(&dev_priv->drm, in cpt_set_fdi_bc_bifurcation()
370 if (IS_IVYBRIDGE(dev_priv)) in intel_fdi_normal_train()
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| H A D | intel_pch_display.c | 50 I915_STATE_WARN(dev_priv, in assert_pch_dp_disabled()
69 I915_STATE_WARN(dev_priv, in assert_pch_hdmi_disabled()
84 I915_STATE_WARN(dev_priv, in assert_pch_ports_disabled()
89 I915_STATE_WARN(dev_priv, in assert_pch_ports_disabled()
122 drm_dbg_kms(&dev_priv->drm, in ibx_sanitize_pch_hdmi_port()
141 drm_dbg_kms(&dev_priv->drm, in ibx_sanitize_pch_dp_port()
180 intel_set_m_n(dev_priv, m_n, in intel_pch_transcoder_set_m1_n1()
191 intel_set_m_n(dev_priv, m_n, in intel_pch_transcoder_set_m2_n2()
202 intel_get_m_n(dev_priv, m_n, in intel_pch_transcoder_get_m1_n1()
213 intel_get_m_n(dev_priv, m_n, in intel_pch_transcoder_get_m2_n2()
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| H A D | intel_hotplug.c | 166 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
170 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
200 drm_info(&dev_priv->drm, in intel_hpd_irq_storm_switch_to_polling()
243 drm_dbg(&dev_priv->drm, in intel_hpd_irq_storm_reenable_work()
520 drm_dbg(&dev_priv->drm, in intel_hpd_irq_handler()
549 drm_WARN_ONCE(&dev_priv->drm, !HAS_GMCH(dev_priv), in intel_hpd_irq_handler()
593 queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv->display.hotplug.dig_port_work); in intel_hpd_irq_handler()
617 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_init()
731 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_poll_disable()
760 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_cancel_work()
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| H A D | intel_combo_phy.c | 98 drm_dbg(&dev_priv->drm, in check_phy_reg()
117 drm_dbg_kms(&dev_priv->drm, in icl_verify_procmon_ref_values()
156 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phy_enabled()
211 else if (IS_ALDERLAKE_S(dev_priv)) in phy_is_master()
213 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) in phy_is_master()
245 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { in icl_combo_phy_verify_state()
318 drm_dbg(&dev_priv->drm, in icl_combo_phys_init()
336 if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && in icl_combo_phys_init()
380 if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) { in icl_combo_phys_uninit()
386 drm_dbg_kms(&dev_priv->drm, in icl_combo_phys_uninit()
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| H A D | intel_display_power.c | 950 if (IS_DG2(dev_priv)) in get_allowed_dc_mask()
956 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in get_allowed_dc_mask()
968 mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || in get_allowed_dc_mask()
1025 get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc); in intel_power_domains_init()
1153 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) in icl_mbus_init()
1206 I915_STATE_WARN(dev_priv, intel_de_read(dev_priv, HSW_PWR_WELL_CTL2), in assert_can_disable_lcpll()
1243 I915_STATE_WARN(dev_priv, intel_irqs_enabled(dev_priv), in assert_can_disable_lcpll()
1445 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); in skl_display_core_init()
1608 if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv)) in tgl_bw_buddy_init()
1658 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); in icl_display_core_init()
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| H A D | intel_lpe_audio.c | 80 #define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display.audio.lpe.platdev != NULL) argument
133 drm_err(&dev_priv->drm, in lpe_audio_platdev_create()
174 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in lpe_audio_irq_init()
187 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in lpe_audio_detect()
197 drm_info(&dev_priv->drm, in lpe_audio_detect()
217 drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->display.audio.lpe.irq); in lpe_audio_setup()
222 drm_err(&dev_priv->drm, in lpe_audio_setup()
228 dev_priv->display.audio.lpe.platdev = lpe_audio_platdev_create(dev_priv); in lpe_audio_setup()
232 drm_err(&dev_priv->drm, in lpe_audio_setup()
264 if (!HAS_LPE_AUDIO(dev_priv)) in intel_lpe_audio_irq_handler()
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| H A D | intel_hotplug_irq.c | 139 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
151 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_hpd_init_pins()
163 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) in intel_hpd_init_pins()
172 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) in intel_hpd_init_pins()
174 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv)) in intel_hpd_init_pins()
361 drm_dbg(&dev_priv->drm, in intel_get_hpd_pins()
420 if (IS_G4X(dev_priv) || in i9xx_hpd_irq_ack()
421 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
459 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_handler()
474 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_hpd_irq_handler()
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| H A D | vlv_dsi.c | 304 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_compute_config()
616 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_port_enable()
741 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_pre_enable()
760 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), in intel_dsi_pre_enable()
875 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
912 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
917 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), in intel_dsi_post_disable()
1519 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_dsi_unprepare()
1780 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
1806 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
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| H A D | intel_dpio_phy.c | 309 drm_err(&dev_priv->drm, in bxt_ddi_phy_set_signal_levels()
336 drm_dbg(&dev_priv->drm, in bxt_ddi_phy_is_enabled()
343 drm_dbg(&dev_priv->drm, in bxt_ddi_phy_is_enabled()
379 dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy); in _bxt_ddi_phy_init()
387 drm_dbg(&dev_priv->drm, in _bxt_ddi_phy_init()
696 vlv_dpio_get(dev_priv); in chv_set_phy_signal_level()
777 vlv_dpio_put(dev_priv); in chv_set_phy_signal_level()
847 vlv_dpio_get(dev_priv); in chv_phy_pre_pll_enable()
902 vlv_dpio_put(dev_priv); in chv_phy_pre_pll_enable()
917 vlv_dpio_get(dev_priv); in chv_phy_pre_encoder_enable()
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| H A D | vlv_dsi_regs.h | 111 #define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004)
112 #define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804)
114 #define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008)
115 #define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808)
213 #define _MIPIA_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb02c)
214 #define _MIPIC_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb82c)
217 #define _MIPIA_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb030)
218 #define _MIPIC_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb830)
229 #define _MIPIA_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb03c)
412 #define _MIPIA_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb104)
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| /openbmc/linux/drivers/gpu/drm/i915/ |
| H A D | i915_irq.c | 193 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) in ivb_parity_work()
230 drm_dbg(&dev_priv->drm, in ivb_parity_work()
243 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); in ivb_parity_work()
671 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_reset()
694 ibx_irq_reset(dev_priv); in ilk_irq_reset()
886 dev_priv->irq_mask = in i8xx_irq_postinstall()
1058 dev_priv->irq_mask = in i915_irq_postinstall()
1185 dev_priv->irq_mask = in i965_irq_postinstall()
1200 if (IS_G4X(dev_priv)) in i965_irq_postinstall()
1291 if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11) in intel_irq_init()
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| H A D | i915_suspend.c | 41 if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { in intel_save_swf()
43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
54 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
57 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
66 if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { in intel_restore_swf()
95 dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB); in i915_save_display()
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| H A D | i915_driver.c | 179 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; in intel_detect_preproduction_hw()
180 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; in intel_detect_preproduction_hw()
181 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
182 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; in intel_detect_preproduction_hw()
183 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; in intel_detect_preproduction_hw()
184 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
185 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
1510 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) in intel_runtime_suspend()
1594 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in intel_runtime_suspend()
1610 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) in intel_runtime_resume()
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| /openbmc/linux/drivers/gpu/drm/vmwgfx/ |
| H A D | vmwgfx_drv.c | 442 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_device_init()
453 dev_priv->fifo = vmw_fifo_create(dev_priv); in vmw_device_init()
462 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); in vmw_device_init()
534 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); in vmw_request_device()
860 dev_priv->drm.dev_private = dev_priv; in vmw_driver_load()
938 dev_priv->memory_size -= dev_priv->vram_size; in vmw_driver_load()
978 dev_priv->texture_max_width = vmw_read(dev_priv, in vmw_driver_load()
982 dev_priv->texture_max_height = vmw_read(dev_priv, in vmw_driver_load()
987 dev_priv->max_primary_mem = dev_priv->vram_size; in vmw_driver_load()
997 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); in vmw_driver_load()
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| H A D | vmwgfx_irq.c | 144 vmw_update_seqno(dev_priv); in vmw_seqno_passed()
148 if (!vmw_has_fences(dev_priv) && vmw_fifo_idle(dev_priv, seqno)) in vmw_seqno_passed()
187 if (dev_priv->cman) { in vmw_fallback_wait()
249 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_add()
260 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_remove()
279 vmw_generic_waiter_add(dev_priv, vmw_irqflag_fence_goal(dev_priv), in vmw_goal_waiter_add()
285 vmw_generic_waiter_remove(dev_priv, vmw_irqflag_fence_goal(dev_priv), in vmw_goal_waiter_remove()
341 drm_err(&dev_priv->drm, in vmw_irq_install()
352 drm_err(&dev_priv->drm, in vmw_irq_install()
356 dev_priv->irqs[i] = ret; in vmw_irq_install()
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| H A D | vmwgfx_cmd.c | 46 if (!dev_priv->has_mob) in vmw_supports_3d()
102 if (!dev_priv->fifo_mem) in vmw_fifo_create()
130 vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MAX, dev_priv->fifo_mem_size); in vmw_fifo_create()
143 drm_info(&dev_priv->drm, in vmw_fifo_create()
150 drm_warn(&dev_priv->drm, in vmw_fifo_create()
183 dev_priv->fifo = NULL; in vmw_fifo_destroy()
369 if (dev_priv->cman) in vmw_cmd_ctx_reserve()
473 if (dev_priv->cman) in vmw_cmd_commit()
488 if (dev_priv->cman) in vmw_cmd_commit_flush()
505 if (dev_priv->cman) in vmw_cmd_flush()
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| /openbmc/linux/drivers/gpu/drm/gma500/ |
| H A D | psb_drv.c | 156 psb_spank(dev_priv); in psb_do_init()
185 if (dev_priv->mmu) { in psb_driver_unload()
190 (dev_priv->mmu), in psb_driver_unload()
247 pg = &dev_priv->gtt; in psb_driver_load()
251 dev_priv->num_pipe = dev_priv->ops->pipes; in psb_driver_load()
255 dev_priv->vdc_reg = in psb_driver_load()
285 dev_priv->aux_reg = dev_priv->vdc_reg; in psb_driver_load()
288 dev_priv->gmbus_reg = dev_priv->aux_reg; in psb_driver_load()
310 dev_priv->gmbus_reg = dev_priv->vdc_reg; in psb_driver_load()
340 if (!dev_priv->mmu) in psb_driver_load()
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| H A D | intel_bios.c | 55 dev_priv->edp.bpp = 18; in parse_edp()
67 dev_priv->edp.bpp = 18; in parse_edp()
70 dev_priv->edp.bpp = 24; in parse_edp()
73 dev_priv->edp.bpp = 30; in parse_edp()
84 dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8, in parse_edp()
85 dev_priv->edp.pps.t9, dev_priv->edp.pps.t10, in parse_edp()
92 dev_priv->edp.lanes = 1; in parse_edp()
95 dev_priv->edp.lanes = 2; in parse_edp()
99 dev_priv->edp.lanes = 4; in parse_edp()
103 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()
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