12b72a38cSJani Nikula /* SPDX-License-Identifier: MIT */ 22b72a38cSJani Nikula /* 32b72a38cSJani Nikula * Copyright © 2022 Intel Corporation 42b72a38cSJani Nikula */ 52b72a38cSJani Nikula 62b72a38cSJani Nikula #ifndef __VLV_DSI_REGS_H__ 72b72a38cSJani Nikula #define __VLV_DSI_REGS_H__ 82b72a38cSJani Nikula 9*e563531aSJani Nikula #include "intel_display_reg_defs.h" 102b72a38cSJani Nikula 112b72a38cSJani Nikula #define VLV_MIPI_BASE VLV_DISPLAY_BASE 122b72a38cSJani Nikula #define BXT_MIPI_BASE 0x60000 132b72a38cSJani Nikula 1490b87cf2SJani Nikula #define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base) 1590b87cf2SJani Nikula 162b72a38cSJani Nikula #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ 172b72a38cSJani Nikula #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 182b72a38cSJani Nikula 192b72a38cSJani Nikula /* BXT MIPI mode configure */ 202b72a38cSJani Nikula #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 212b72a38cSJani Nikula #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 222b72a38cSJani Nikula #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ 232b72a38cSJani Nikula _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) 242b72a38cSJani Nikula 252b72a38cSJani Nikula #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC 262b72a38cSJani Nikula #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC 272b72a38cSJani Nikula #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ 282b72a38cSJani Nikula _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) 292b72a38cSJani Nikula 302b72a38cSJani Nikula #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 312b72a38cSJani Nikula #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 322b72a38cSJani Nikula #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ 332b72a38cSJani Nikula _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) 342b72a38cSJani Nikula 352b72a38cSJani Nikula #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) 362b72a38cSJani Nikula #define STAP_SELECT (1 << 0) 372b72a38cSJani Nikula 382b72a38cSJani Nikula #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) 392b72a38cSJani Nikula #define HS_IO_CTRL_SELECT (1 << 0) 402b72a38cSJani Nikula 412b72a38cSJani Nikula #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 422b72a38cSJani Nikula #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 432b72a38cSJani Nikula #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 442b72a38cSJani Nikula 452b72a38cSJani Nikula /* BXT port control */ 462b72a38cSJani Nikula #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 472b72a38cSJani Nikula #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 482b72a38cSJani Nikula #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) 492b72a38cSJani Nikula 502b72a38cSJani Nikula #define DPI_ENABLE (1 << 31) /* A + C */ 512b72a38cSJani Nikula #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 522b72a38cSJani Nikula #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 532b72a38cSJani Nikula #define DUAL_LINK_MODE_SHIFT 26 542b72a38cSJani Nikula #define DUAL_LINK_MODE_MASK (1 << 26) 552b72a38cSJani Nikula #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 562b72a38cSJani Nikula #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 572b72a38cSJani Nikula #define DITHERING_ENABLE (1 << 25) /* A + C */ 582b72a38cSJani Nikula #define FLOPPED_HSTX (1 << 23) 592b72a38cSJani Nikula #define DE_INVERT (1 << 19) /* XXX */ 602b72a38cSJani Nikula #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 612b72a38cSJani Nikula #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 622b72a38cSJani Nikula #define AFE_LATCHOUT (1 << 17) 632b72a38cSJani Nikula #define LP_OUTPUT_HOLD (1 << 16) 642b72a38cSJani Nikula #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 652b72a38cSJani Nikula #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 662b72a38cSJani Nikula #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 672b72a38cSJani Nikula #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 682b72a38cSJani Nikula #define CSB_SHIFT 9 692b72a38cSJani Nikula #define CSB_MASK (3 << 9) 702b72a38cSJani Nikula #define CSB_20MHZ (0 << 9) 712b72a38cSJani Nikula #define CSB_10MHZ (1 << 9) 722b72a38cSJani Nikula #define CSB_40MHZ (2 << 9) 732b72a38cSJani Nikula #define BANDGAP_MASK (1 << 8) 742b72a38cSJani Nikula #define BANDGAP_PNW_CIRCUIT (0 << 8) 752b72a38cSJani Nikula #define BANDGAP_LNC_CIRCUIT (1 << 8) 762b72a38cSJani Nikula #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 772b72a38cSJani Nikula #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 782b72a38cSJani Nikula #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 792b72a38cSJani Nikula #define TEARING_EFFECT_SHIFT 2 /* A + C */ 802b72a38cSJani Nikula #define TEARING_EFFECT_MASK (3 << 2) 812b72a38cSJani Nikula #define TEARING_EFFECT_OFF (0 << 2) 822b72a38cSJani Nikula #define TEARING_EFFECT_DSI (1 << 2) 832b72a38cSJani Nikula #define TEARING_EFFECT_GPIO (2 << 2) 842b72a38cSJani Nikula #define LANE_CONFIGURATION_SHIFT 0 852b72a38cSJani Nikula #define LANE_CONFIGURATION_MASK (3 << 0) 862b72a38cSJani Nikula #define LANE_CONFIGURATION_4LANE (0 << 0) 872b72a38cSJani Nikula #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 882b72a38cSJani Nikula #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 892b72a38cSJani Nikula 902b72a38cSJani Nikula #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 912b72a38cSJani Nikula #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 922b72a38cSJani Nikula #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 932b72a38cSJani Nikula #define TEARING_EFFECT_DELAY_SHIFT 0 942b72a38cSJani Nikula #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 952b72a38cSJani Nikula 962b72a38cSJani Nikula /* XXX: all bits reserved */ 972b72a38cSJani Nikula #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 982b72a38cSJani Nikula 992b72a38cSJani Nikula /* MIPI DSI Controller and D-PHY registers */ 1002b72a38cSJani Nikula 10190b87cf2SJani Nikula #define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000) 10290b87cf2SJani Nikula #define _MIPIC_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb800) 1032b72a38cSJani Nikula #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) 1042b72a38cSJani Nikula #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 1052b72a38cSJani Nikula #define ULPS_STATE_MASK (3 << 1) 1062b72a38cSJani Nikula #define ULPS_STATE_ENTER (2 << 1) 1072b72a38cSJani Nikula #define ULPS_STATE_EXIT (1 << 1) 1082b72a38cSJani Nikula #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 1092b72a38cSJani Nikula #define DEVICE_READY (1 << 0) 1102b72a38cSJani Nikula 11190b87cf2SJani Nikula #define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004) 11290b87cf2SJani Nikula #define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804) 1132b72a38cSJani Nikula #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) 11490b87cf2SJani Nikula #define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008) 11590b87cf2SJani Nikula #define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808) 1162b72a38cSJani Nikula #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) 1172b72a38cSJani Nikula #define TEARING_EFFECT (1 << 31) 1182b72a38cSJani Nikula #define SPL_PKT_SENT_INTERRUPT (1 << 30) 1192b72a38cSJani Nikula #define GEN_READ_DATA_AVAIL (1 << 29) 1202b72a38cSJani Nikula #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 1212b72a38cSJani Nikula #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 1222b72a38cSJani Nikula #define RX_PROT_VIOLATION (1 << 26) 1232b72a38cSJani Nikula #define RX_INVALID_TX_LENGTH (1 << 25) 1242b72a38cSJani Nikula #define ACK_WITH_NO_ERROR (1 << 24) 1252b72a38cSJani Nikula #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 1262b72a38cSJani Nikula #define LP_RX_TIMEOUT (1 << 22) 1272b72a38cSJani Nikula #define HS_TX_TIMEOUT (1 << 21) 1282b72a38cSJani Nikula #define DPI_FIFO_UNDERRUN (1 << 20) 1292b72a38cSJani Nikula #define LOW_CONTENTION (1 << 19) 1302b72a38cSJani Nikula #define HIGH_CONTENTION (1 << 18) 1312b72a38cSJani Nikula #define TXDSI_VC_ID_INVALID (1 << 17) 1322b72a38cSJani Nikula #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 1332b72a38cSJani Nikula #define TXCHECKSUM_ERROR (1 << 15) 1342b72a38cSJani Nikula #define TXECC_MULTIBIT_ERROR (1 << 14) 1352b72a38cSJani Nikula #define TXECC_SINGLE_BIT_ERROR (1 << 13) 1362b72a38cSJani Nikula #define TXFALSE_CONTROL_ERROR (1 << 12) 1372b72a38cSJani Nikula #define RXDSI_VC_ID_INVALID (1 << 11) 1382b72a38cSJani Nikula #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 1392b72a38cSJani Nikula #define RXCHECKSUM_ERROR (1 << 9) 1402b72a38cSJani Nikula #define RXECC_MULTIBIT_ERROR (1 << 8) 1412b72a38cSJani Nikula #define RXECC_SINGLE_BIT_ERROR (1 << 7) 1422b72a38cSJani Nikula #define RXFALSE_CONTROL_ERROR (1 << 6) 1432b72a38cSJani Nikula #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 1442b72a38cSJani Nikula #define RX_LP_TX_SYNC_ERROR (1 << 4) 1452b72a38cSJani Nikula #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 1462b72a38cSJani Nikula #define RXEOT_SYNC_ERROR (1 << 2) 1472b72a38cSJani Nikula #define RXSOT_SYNC_ERROR (1 << 1) 1482b72a38cSJani Nikula #define RXSOT_ERROR (1 << 0) 1492b72a38cSJani Nikula 15090b87cf2SJani Nikula #define _MIPIA_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb00c) 15190b87cf2SJani Nikula #define _MIPIC_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb80c) 1522b72a38cSJani Nikula #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) 1532b72a38cSJani Nikula #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 1542b72a38cSJani Nikula #define CMD_MODE_NOT_SUPPORTED (0 << 13) 1552b72a38cSJani Nikula #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 1562b72a38cSJani Nikula #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 1572b72a38cSJani Nikula #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 1582b72a38cSJani Nikula #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 1592b72a38cSJani Nikula #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 1602b72a38cSJani Nikula #define VID_MODE_FORMAT_MASK (0xf << 7) 1612b72a38cSJani Nikula #define VID_MODE_NOT_SUPPORTED (0 << 7) 1622b72a38cSJani Nikula #define VID_MODE_FORMAT_RGB565 (1 << 7) 1632b72a38cSJani Nikula #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) 1642b72a38cSJani Nikula #define VID_MODE_FORMAT_RGB666 (3 << 7) 1652b72a38cSJani Nikula #define VID_MODE_FORMAT_RGB888 (4 << 7) 1662b72a38cSJani Nikula #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 1672b72a38cSJani Nikula #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 1682b72a38cSJani Nikula #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 1692b72a38cSJani Nikula #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 1702b72a38cSJani Nikula #define DATA_LANES_PRG_REG_SHIFT 0 1712b72a38cSJani Nikula #define DATA_LANES_PRG_REG_MASK (7 << 0) 1722b72a38cSJani Nikula 17390b87cf2SJani Nikula #define _MIPIA_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb010) 17490b87cf2SJani Nikula #define _MIPIC_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb810) 1752b72a38cSJani Nikula #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) 1762b72a38cSJani Nikula #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 1772b72a38cSJani Nikula 17890b87cf2SJani Nikula #define _MIPIA_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb014) 17990b87cf2SJani Nikula #define _MIPIC_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb814) 1802b72a38cSJani Nikula #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) 1812b72a38cSJani Nikula #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 1822b72a38cSJani Nikula 18390b87cf2SJani Nikula #define _MIPIA_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb018) 18490b87cf2SJani Nikula #define _MIPIC_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb818) 1852b72a38cSJani Nikula #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 1862b72a38cSJani Nikula #define TURN_AROUND_TIMEOUT_MASK 0x3f 1872b72a38cSJani Nikula 18890b87cf2SJani Nikula #define _MIPIA_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb01c) 18990b87cf2SJani Nikula #define _MIPIC_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb81c) 1902b72a38cSJani Nikula #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 1912b72a38cSJani Nikula #define DEVICE_RESET_TIMER_MASK 0xffff 1922b72a38cSJani Nikula 19390b87cf2SJani Nikula #define _MIPIA_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb020) 19490b87cf2SJani Nikula #define _MIPIC_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb820) 1952b72a38cSJani Nikula #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) 1962b72a38cSJani Nikula #define VERTICAL_ADDRESS_SHIFT 16 1972b72a38cSJani Nikula #define VERTICAL_ADDRESS_MASK (0xffff << 16) 1982b72a38cSJani Nikula #define HORIZONTAL_ADDRESS_SHIFT 0 1992b72a38cSJani Nikula #define HORIZONTAL_ADDRESS_MASK 0xffff 2002b72a38cSJani Nikula 20190b87cf2SJani Nikula #define _MIPIA_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb024) 20290b87cf2SJani Nikula #define _MIPIC_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb824) 2032b72a38cSJani Nikula #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 2042b72a38cSJani Nikula #define DBI_FIFO_EMPTY_HALF (0 << 0) 2052b72a38cSJani Nikula #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 2062b72a38cSJani Nikula #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 2072b72a38cSJani Nikula 2082b72a38cSJani Nikula /* regs below are bits 15:0 */ 20990b87cf2SJani Nikula #define _MIPIA_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb028) 21090b87cf2SJani Nikula #define _MIPIC_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb828) 2112b72a38cSJani Nikula #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 2122b72a38cSJani Nikula 21390b87cf2SJani Nikula #define _MIPIA_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb02c) 21490b87cf2SJani Nikula #define _MIPIC_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb82c) 2152b72a38cSJani Nikula #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) 2162b72a38cSJani Nikula 21790b87cf2SJani Nikula #define _MIPIA_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb030) 21890b87cf2SJani Nikula #define _MIPIC_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb830) 2192b72a38cSJani Nikula #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) 2202b72a38cSJani Nikula 22190b87cf2SJani Nikula #define _MIPIA_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb034) 22290b87cf2SJani Nikula #define _MIPIC_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb834) 2232b72a38cSJani Nikula #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 2242b72a38cSJani Nikula 22590b87cf2SJani Nikula #define _MIPIA_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb038) 22690b87cf2SJani Nikula #define _MIPIC_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb838) 2272b72a38cSJani Nikula #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 2282b72a38cSJani Nikula 22990b87cf2SJani Nikula #define _MIPIA_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb03c) 23090b87cf2SJani Nikula #define _MIPIC_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb83c) 2312b72a38cSJani Nikula #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) 2322b72a38cSJani Nikula 23390b87cf2SJani Nikula #define _MIPIA_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb040) 23490b87cf2SJani Nikula #define _MIPIC_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb840) 2352b72a38cSJani Nikula #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) 2362b72a38cSJani Nikula 23790b87cf2SJani Nikula #define _MIPIA_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb044) 23890b87cf2SJani Nikula #define _MIPIC_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb844) 2392b72a38cSJani Nikula #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 2402b72a38cSJani Nikula 24190b87cf2SJani Nikula #define _MIPIA_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb048) 24290b87cf2SJani Nikula #define _MIPIC_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb848) 2432b72a38cSJani Nikula #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) 2442b72a38cSJani Nikula #define DPI_LP_MODE (1 << 6) 2452b72a38cSJani Nikula #define BACKLIGHT_OFF (1 << 5) 2462b72a38cSJani Nikula #define BACKLIGHT_ON (1 << 4) 2472b72a38cSJani Nikula #define COLOR_MODE_OFF (1 << 3) 2482b72a38cSJani Nikula #define COLOR_MODE_ON (1 << 2) 2492b72a38cSJani Nikula #define TURN_ON (1 << 1) 2502b72a38cSJani Nikula #define SHUTDOWN (1 << 0) 2512b72a38cSJani Nikula 25290b87cf2SJani Nikula #define _MIPIA_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb04c) 25390b87cf2SJani Nikula #define _MIPIC_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb84c) 2542b72a38cSJani Nikula #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) 2552b72a38cSJani Nikula #define COMMAND_BYTE_SHIFT 0 2562b72a38cSJani Nikula #define COMMAND_BYTE_MASK (0x3f << 0) 2572b72a38cSJani Nikula 25890b87cf2SJani Nikula #define _MIPIA_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb050) 25990b87cf2SJani Nikula #define _MIPIC_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb850) 2602b72a38cSJani Nikula #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) 2612b72a38cSJani Nikula #define MASTER_INIT_TIMER_SHIFT 0 2622b72a38cSJani Nikula #define MASTER_INIT_TIMER_MASK (0xffff << 0) 2632b72a38cSJani Nikula 26490b87cf2SJani Nikula #define _MIPIA_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb054) 26590b87cf2SJani Nikula #define _MIPIC_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb854) 2662b72a38cSJani Nikula #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ 2672b72a38cSJani Nikula _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 2682b72a38cSJani Nikula #define MAX_RETURN_PKT_SIZE_SHIFT 0 2692b72a38cSJani Nikula #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 2702b72a38cSJani Nikula 27190b87cf2SJani Nikula #define _MIPIA_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb058) 27290b87cf2SJani Nikula #define _MIPIC_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb858) 2732b72a38cSJani Nikula #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 2742b72a38cSJani Nikula #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 2752b72a38cSJani Nikula #define DISABLE_VIDEO_BTA (1 << 3) 2762b72a38cSJani Nikula #define IP_TG_CONFIG (1 << 2) 2772b72a38cSJani Nikula #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 2782b72a38cSJani Nikula #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 2792b72a38cSJani Nikula #define VIDEO_MODE_BURST (3 << 0) 2802b72a38cSJani Nikula 28190b87cf2SJani Nikula #define _MIPIA_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb05c) 28290b87cf2SJani Nikula #define _MIPIC_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb85c) 2832b72a38cSJani Nikula #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) 2842b72a38cSJani Nikula #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) 2852b72a38cSJani Nikula #define BXT_DPHY_DEFEATURE_EN (1 << 8) 2862b72a38cSJani Nikula #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 2872b72a38cSJani Nikula #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 2882b72a38cSJani Nikula #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 2892b72a38cSJani Nikula #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 2902b72a38cSJani Nikula #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 2912b72a38cSJani Nikula #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 2922b72a38cSJani Nikula #define CLOCKSTOP (1 << 1) 2932b72a38cSJani Nikula #define EOT_DISABLE (1 << 0) 2942b72a38cSJani Nikula 29590b87cf2SJani Nikula #define _MIPIA_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb060) 29690b87cf2SJani Nikula #define _MIPIC_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb860) 2972b72a38cSJani Nikula #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) 2982b72a38cSJani Nikula #define LP_BYTECLK_SHIFT 0 2992b72a38cSJani Nikula #define LP_BYTECLK_MASK (0xffff << 0) 3002b72a38cSJani Nikula 30190b87cf2SJani Nikula #define _MIPIA_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb0a4) 30290b87cf2SJani Nikula #define _MIPIC_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb8a4) 3032b72a38cSJani Nikula #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) 3042b72a38cSJani Nikula 30590b87cf2SJani Nikula #define _MIPIA_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb098) 30690b87cf2SJani Nikula #define _MIPIC_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb898) 3072b72a38cSJani Nikula #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) 3082b72a38cSJani Nikula 3092b72a38cSJani Nikula /* bits 31:0 */ 31090b87cf2SJani Nikula #define _MIPIA_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb064) 31190b87cf2SJani Nikula #define _MIPIC_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb864) 3122b72a38cSJani Nikula #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) 3132b72a38cSJani Nikula 3142b72a38cSJani Nikula /* bits 31:0 */ 31590b87cf2SJani Nikula #define _MIPIA_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb068) 31690b87cf2SJani Nikula #define _MIPIC_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb868) 3172b72a38cSJani Nikula #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) 3182b72a38cSJani Nikula 31990b87cf2SJani Nikula #define _MIPIA_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb06c) 32090b87cf2SJani Nikula #define _MIPIC_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb86c) 3212b72a38cSJani Nikula #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) 32290b87cf2SJani Nikula #define _MIPIA_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb070) 32390b87cf2SJani Nikula #define _MIPIC_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb870) 3242b72a38cSJani Nikula #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) 3252b72a38cSJani Nikula #define LONG_PACKET_WORD_COUNT_SHIFT 8 3262b72a38cSJani Nikula #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 3272b72a38cSJani Nikula #define SHORT_PACKET_PARAM_SHIFT 8 3282b72a38cSJani Nikula #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 3292b72a38cSJani Nikula #define VIRTUAL_CHANNEL_SHIFT 6 3302b72a38cSJani Nikula #define VIRTUAL_CHANNEL_MASK (3 << 6) 3312b72a38cSJani Nikula #define DATA_TYPE_SHIFT 0 3322b72a38cSJani Nikula #define DATA_TYPE_MASK (0x3f << 0) 3332b72a38cSJani Nikula /* data type values, see include/video/mipi_display.h */ 3342b72a38cSJani Nikula 33590b87cf2SJani Nikula #define _MIPIA_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb074) 33690b87cf2SJani Nikula #define _MIPIC_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb874) 3372b72a38cSJani Nikula #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) 3382b72a38cSJani Nikula #define DPI_FIFO_EMPTY (1 << 28) 3392b72a38cSJani Nikula #define DBI_FIFO_EMPTY (1 << 27) 3402b72a38cSJani Nikula #define LP_CTRL_FIFO_EMPTY (1 << 26) 3412b72a38cSJani Nikula #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 3422b72a38cSJani Nikula #define LP_CTRL_FIFO_FULL (1 << 24) 3432b72a38cSJani Nikula #define HS_CTRL_FIFO_EMPTY (1 << 18) 3442b72a38cSJani Nikula #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 3452b72a38cSJani Nikula #define HS_CTRL_FIFO_FULL (1 << 16) 3462b72a38cSJani Nikula #define LP_DATA_FIFO_EMPTY (1 << 10) 3472b72a38cSJani Nikula #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 3482b72a38cSJani Nikula #define LP_DATA_FIFO_FULL (1 << 8) 3492b72a38cSJani Nikula #define HS_DATA_FIFO_EMPTY (1 << 2) 3502b72a38cSJani Nikula #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 3512b72a38cSJani Nikula #define HS_DATA_FIFO_FULL (1 << 0) 3522b72a38cSJani Nikula 35390b87cf2SJani Nikula #define _MIPIA_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb078) 35490b87cf2SJani Nikula #define _MIPIC_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb878) 3552b72a38cSJani Nikula #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 3562b72a38cSJani Nikula #define DBI_HS_LP_MODE_MASK (1 << 0) 3572b72a38cSJani Nikula #define DBI_LP_MODE (1 << 0) 3582b72a38cSJani Nikula #define DBI_HS_MODE (0 << 0) 3592b72a38cSJani Nikula 36090b87cf2SJani Nikula #define _MIPIA_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb080) 36190b87cf2SJani Nikula #define _MIPIC_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb880) 3622b72a38cSJani Nikula #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) 3632b72a38cSJani Nikula #define EXIT_ZERO_COUNT_SHIFT 24 3642b72a38cSJani Nikula #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 3652b72a38cSJani Nikula #define TRAIL_COUNT_SHIFT 16 3662b72a38cSJani Nikula #define TRAIL_COUNT_MASK (0x1f << 16) 3672b72a38cSJani Nikula #define CLK_ZERO_COUNT_SHIFT 8 3682b72a38cSJani Nikula #define CLK_ZERO_COUNT_MASK (0xff << 8) 3692b72a38cSJani Nikula #define PREPARE_COUNT_SHIFT 0 3702b72a38cSJani Nikula #define PREPARE_COUNT_MASK (0x3f << 0) 3712b72a38cSJani Nikula 37290b87cf2SJani Nikula #define _MIPIA_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb084) 37390b87cf2SJani Nikula #define _MIPIC_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb884) 3742b72a38cSJani Nikula #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) 3752b72a38cSJani Nikula 37690b87cf2SJani Nikula #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb088) 37790b87cf2SJani Nikula #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb888) 3782b72a38cSJani Nikula #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 3792b72a38cSJani Nikula #define LP_HS_SSW_CNT_SHIFT 16 3802b72a38cSJani Nikula #define LP_HS_SSW_CNT_MASK (0xffff << 16) 3812b72a38cSJani Nikula #define HS_LP_PWR_SW_CNT_SHIFT 0 3822b72a38cSJani Nikula #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 3832b72a38cSJani Nikula 38490b87cf2SJani Nikula #define _MIPIA_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb08c) 38590b87cf2SJani Nikula #define _MIPIC_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb88c) 3862b72a38cSJani Nikula #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 3872b72a38cSJani Nikula #define STOP_STATE_STALL_COUNTER_SHIFT 0 3882b72a38cSJani Nikula #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 3892b72a38cSJani Nikula 39090b87cf2SJani Nikula #define _MIPIA_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb090) 39190b87cf2SJani Nikula #define _MIPIC_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb890) 3922b72a38cSJani Nikula #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 39390b87cf2SJani Nikula #define _MIPIA_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb094) 39490b87cf2SJani Nikula #define _MIPIC_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb894) 3952b72a38cSJani Nikula #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) 3962b72a38cSJani Nikula #define RX_CONTENTION_DETECTED (1 << 0) 3972b72a38cSJani Nikula 3982b72a38cSJani Nikula /* XXX: only pipe A ?!? */ 39990b87cf2SJani Nikula #define MIPIA_DBI_TYPEC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb100) 4002b72a38cSJani Nikula #define DBI_TYPEC_ENABLE (1 << 31) 4012b72a38cSJani Nikula #define DBI_TYPEC_WIP (1 << 30) 4022b72a38cSJani Nikula #define DBI_TYPEC_OPTION_SHIFT 28 4032b72a38cSJani Nikula #define DBI_TYPEC_OPTION_MASK (3 << 28) 4042b72a38cSJani Nikula #define DBI_TYPEC_FREQ_SHIFT 24 4052b72a38cSJani Nikula #define DBI_TYPEC_FREQ_MASK (0xf << 24) 4062b72a38cSJani Nikula #define DBI_TYPEC_OVERRIDE (1 << 8) 4072b72a38cSJani Nikula #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 4082b72a38cSJani Nikula #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 4092b72a38cSJani Nikula 4102b72a38cSJani Nikula /* MIPI adapter registers */ 4112b72a38cSJani Nikula 41290b87cf2SJani Nikula #define _MIPIA_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb104) 41390b87cf2SJani Nikula #define _MIPIC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb904) 4142b72a38cSJani Nikula #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) 4152b72a38cSJani Nikula #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 4162b72a38cSJani Nikula #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 4172b72a38cSJani Nikula #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 4182b72a38cSJani Nikula #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 4192b72a38cSJani Nikula #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 4202b72a38cSJani Nikula #define READ_REQUEST_PRIORITY_SHIFT 3 4212b72a38cSJani Nikula #define READ_REQUEST_PRIORITY_MASK (3 << 3) 4222b72a38cSJani Nikula #define READ_REQUEST_PRIORITY_LOW (0 << 3) 4232b72a38cSJani Nikula #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 4242b72a38cSJani Nikula #define RGB_FLIP_TO_BGR (1 << 2) 4252b72a38cSJani Nikula 4262b72a38cSJani Nikula #define BXT_PIPE_SELECT_SHIFT 7 4272b72a38cSJani Nikula #define BXT_PIPE_SELECT_MASK (7 << 7) 4282b72a38cSJani Nikula #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) 4292b72a38cSJani Nikula #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */ 4302b72a38cSJani Nikula #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */ 4312b72a38cSJani Nikula #define GLK_MIPIIO_RESET_RELEASED (1 << 28) 4322b72a38cSJani Nikula #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */ 4332b72a38cSJani Nikula #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */ 4342b72a38cSJani Nikula #define GLK_LP_WAKE (1 << 22) 4352b72a38cSJani Nikula #define GLK_LP11_LOW_PWR_MODE (1 << 21) 4362b72a38cSJani Nikula #define GLK_LP00_LOW_PWR_MODE (1 << 20) 4372b72a38cSJani Nikula #define GLK_FIREWALL_ENABLE (1 << 16) 4382b72a38cSJani Nikula #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) 4392b72a38cSJani Nikula #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 4402b72a38cSJani Nikula #define BXT_DSC_ENABLE (1 << 3) 4412b72a38cSJani Nikula #define BXT_RGB_FLIP (1 << 2) 4422b72a38cSJani Nikula #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ 4432b72a38cSJani Nikula #define GLK_MIPIIO_ENABLE (1 << 0) 4442b72a38cSJani Nikula 44590b87cf2SJani Nikula #define _MIPIA_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb108) 44690b87cf2SJani Nikula #define _MIPIC_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb908) 4472b72a38cSJani Nikula #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) 4482b72a38cSJani Nikula #define DATA_MEM_ADDRESS_SHIFT 5 4492b72a38cSJani Nikula #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 4502b72a38cSJani Nikula #define DATA_VALID (1 << 0) 4512b72a38cSJani Nikula 45290b87cf2SJani Nikula #define _MIPIA_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb10c) 45390b87cf2SJani Nikula #define _MIPIC_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb90c) 4542b72a38cSJani Nikula #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) 4552b72a38cSJani Nikula #define DATA_LENGTH_SHIFT 0 4562b72a38cSJani Nikula #define DATA_LENGTH_MASK (0xfffff << 0) 4572b72a38cSJani Nikula 45890b87cf2SJani Nikula #define _MIPIA_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb110) 45990b87cf2SJani Nikula #define _MIPIC_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb910) 4602b72a38cSJani Nikula #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 4612b72a38cSJani Nikula #define COMMAND_MEM_ADDRESS_SHIFT 5 4622b72a38cSJani Nikula #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 4632b72a38cSJani Nikula #define AUTO_PWG_ENABLE (1 << 2) 4642b72a38cSJani Nikula #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 4652b72a38cSJani Nikula #define COMMAND_VALID (1 << 0) 4662b72a38cSJani Nikula 46790b87cf2SJani Nikula #define _MIPIA_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb114) 46890b87cf2SJani Nikula #define _MIPIC_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb914) 4692b72a38cSJani Nikula #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) 4702b72a38cSJani Nikula #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 4712b72a38cSJani Nikula #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 4722b72a38cSJani Nikula 47390b87cf2SJani Nikula #define _MIPIA_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb118) 47490b87cf2SJani Nikula #define _MIPIC_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb918) 4752b72a38cSJani Nikula #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 4762b72a38cSJani Nikula 47790b87cf2SJani Nikula #define _MIPIA_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb138) 47890b87cf2SJani Nikula #define _MIPIC_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb938) 4792b72a38cSJani Nikula #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 4802b72a38cSJani Nikula #define READ_DATA_VALID(n) (1 << (n)) 4812b72a38cSJani Nikula 4822b72a38cSJani Nikula #endif /* __VLV_DSI_REGS_H__ */ 483