| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 109 .dcfclk_mhz = 1434.0,
281 if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz) in sort_entries_with_same_bw()
324 curr_clk_limit->dcfclk_mhz = max_clk_limit->dcfclk_mhz; in override_max_clk_values()
365 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz) in build_synthetic_soc_states()
366 max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_synthetic_soc_states()
445 entry.dcfclk_mhz = max_clk_data.dcfclk_mhz; in build_synthetic_soc_states()
455 entry.dcfclk_mhz = 0; in build_synthetic_soc_states()
493 if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz || in build_synthetic_soc_states()
503 max_dc_limits_entry.dcfclk_mhz = max_clk_data.dcfclk_mhz; in build_synthetic_soc_states()
561 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && in build_synthetic_soc_states()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 200 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box() local
224 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn302_fpu_update_bw_bounding_box()
225 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
234 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
265 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
303 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
310 dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn302_fpu_update_bw_bounding_box()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 196 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box() local
220 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn303_fpu_update_bw_bounding_box()
221 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
230 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
278 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
282 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
292 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
298 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
305 dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn303_fpu_update_bw_bounding_box()
306 dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; in dcn303_fpu_update_bw_bounding_box()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 119 .dcfclk_mhz = 400.0,
131 .dcfclk_mhz = 400.0,
143 .dcfclk_mhz = 608.0,
155 .dcfclk_mhz = 676.0,
167 .dcfclk_mhz = 810.0,
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
344 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn301_update_bw_bounding_box()
351 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn301_update_bw_bounding_box()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 223 .dcfclk_mhz = 560.0,
234 .dcfclk_mhz = 694.0,
245 .dcfclk_mhz = 875.0,
334 .dcfclk_mhz = 560.0,
445 .dcfclk_mhz = 560.0,
456 .dcfclk_mhz = 694.0,
467 .dcfclk_mhz = 875.0,
1951 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) in dcn20_cap_soc_clocks()
2212 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
2378 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz; in construct_low_pstate_lvl()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 218 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn314_update_bw_bounding_box_fpu()
231 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn314_update_bw_bounding_box_fpu()
233 clock_limits[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn314_update_bw_bounding_box_fpu()
235 clock_limits[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; in dcn314_update_bw_bounding_box_fpu()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 120 .dcfclk_mhz = 1564.0,
2385 if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz) in sort_entries_with_same_bw()
2428 curr_clk_limit->dcfclk_mhz = max_clk_limit->dcfclk_mhz; in override_max_clk_values()
2469 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz) in build_synthetic_soc_states()
2470 max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_synthetic_soc_states()
2549 entry.dcfclk_mhz = max_clk_data.dcfclk_mhz; in build_synthetic_soc_states()
2559 entry.dcfclk_mhz = 0; in build_synthetic_soc_states()
2597 if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz || in build_synthetic_soc_states()
2607 max_dc_limits_entry.dcfclk_mhz = max_clk_data.dcfclk_mhz; in build_synthetic_soc_states()
2663 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && in build_synthetic_soc_states()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 506 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
612 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()
621 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box()
689 dcn3_15_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn315_update_bw_bounding_box()
751 if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <= in dcn316_update_bw_bounding_box()
752 clk_table->entries[i].dcfclk_mhz) { in dcn316_update_bw_bounding_box()
766 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn316_update_bw_bounding_box()
768 s[i].dcfclk_mhz < in dcn316_update_bw_bounding_box()
769 dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn316_update_bw_bounding_box()
771 s[i].dcfclk_mhz = in dcn316_update_bw_bounding_box()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 404 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn315_build_watermark_ranges()
407 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn315_build_watermark_ranges()
504 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn315_clk_mgr_helper_populate_bw_params()
514 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; in dcn315_clk_mgr_helper_populate_bw_params()
526 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[0]; in dcn315_clk_mgr_helper_populate_bw_params()
546 if (!bw_params->clk_table.entries[i].dcfclk_mhz) in dcn315_clk_mgr_helper_populate_bw_params()
547 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
566 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); in dcn315_clk_mgr_helper_populate_bw_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 409 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in vg_build_watermark_ranges()
412 bw_params->clk_table.entries[i].dcfclk_mhz; in vg_build_watermark_ranges()
497 .dcfclk_mhz = 400,
504 .dcfclk_mhz = 483,
511 .dcfclk_mhz = 602,
518 .dcfclk_mhz = 738,
590 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfP… in vg_clk_mgr_helper_populate_bw_params()
595 …bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, VG_NUM_DCF… in vg_clk_mgr_helper_populate_bw_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 459 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn314_build_watermark_ranges()
462 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn314_build_watermark_ranges()
614 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn314_clk_mgr_helper_populate_bw_params()
625 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; in dcn314_clk_mgr_helper_populate_bw_params()
641 …bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK… in dcn314_clk_mgr_helper_populate_bw_params()
670 if (!bw_params->clk_table.entries[i].dcfclk_mhz) in dcn314_clk_mgr_helper_populate_bw_params()
671 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
685 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); in dcn314_clk_mgr_helper_populate_bw_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 477 …der_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in build_watermark_ranges()
479 …ges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_watermark_ranges()
580 .dcfclk_mhz = 400,
587 .dcfclk_mhz = 483,
594 .dcfclk_mhz = 602,
601 .dcfclk_mhz = 738,
668 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 425 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
435 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
451 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
606 dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_update_max_clk()
642 unsigned int *dcfclk_mhz, in dcn30_fpu_update_bw_bounding_box() argument
654 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn30_fpu_update_bw_bounding_box()
655 dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; in dcn30_fpu_update_bw_bounding_box()
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| H A D | dcn30_fpu.h | 63 unsigned int *dcfclk_mhz,
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 29 uint32_t dcfclk_mhz; member
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 159 double dcfclk_mhz; member
552 double dcfclk_mhz; member
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| H A D | display_mode_lib.c | 281 dml_print("DML PARAMS: dcfclk_mhz = %3.2f\n", clks_cfg->dcfclk_mhz); in dml_log_pipe_params()
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| H A D | display_mode_vba.c | 380 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
395 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
1093 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz; in ModeSupportAndSystemConfiguration()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_resource.c | 144 .dcfclk_mhz = 1000.0,
155 .dcfclk_mhz = 1000.0,
166 .dcfclk_mhz = 1000.0,
177 .dcfclk_mhz = 1000.0,
188 .dcfclk_mhz = 1000.0,
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.c | 2094 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local
2117 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz) in dcn30_update_bw_bounding_box()
2118 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2155 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn30_update_bw_bounding_box()
2156 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2176 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2180 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
2189 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2195 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
2201 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts); in dcn30_update_bw_bounding_box()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 366 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn316_build_watermark_ranges()
369 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn316_build_watermark_ranges()
534 bw_params->clk_table.entries[i].dcfclk_mhz = temp; in dcn316_clk_mgr_helper_populate_bw_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 86 unsigned int dcfclk_mhz; member
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 444 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn31_build_watermark_ranges()
447 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn31_build_watermark_ranges()
607 …bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClo… in dcn31_clk_mgr_helper_populate_bw_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 183 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn32_init_clocks()
185 …clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_init_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 133 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
|