120 			.dcfclk_mhz = 1564.0,
182 	uint16_t min_dcfclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;  in dcn32_build_wm_range_table_fpu()
184 …nt16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;  in dcn32_build_wm_range_table_fpu()
192 …entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;  in dcn32_build_wm_range_table_fpu()
450 	sdp_bw_kbytes_sec = entry->dcfclk_mhz *  in calculate_net_bw_in_kbytes_sec()
467 	if (entry->dcfclk_mhz > 0) {  in get_optimal_ntuple()
468 …float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_i…  in get_optimal_ntuple()
476 …entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ide…  in get_optimal_ntuple()
484 …entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal…  in get_optimal_ntuple()
578 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;  in dcn32_set_phantom_stream_timing()
1965 	double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;  in dcn32_calculate_wm_and_dlg_fpu()
2077 		dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz;  in dcn32_calculate_wm_and_dlg_fpu()
2082 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;  in dcn32_calculate_wm_and_dlg_fpu()
2147 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;  in dcn32_calculate_wm_and_dlg_fpu()
2151 		pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching;  in dcn32_calculate_wm_and_dlg_fpu()
2323 		if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)  in dcn32_patch_dpm_table()
2324 			max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;  in dcn32_patch_dpm_table()
2346 		bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;  in dcn32_patch_dpm_table()
2385 					if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)  in sort_entries_with_same_bw()
2427 	if (max_clk_limit->dcfclk_mhz != 0)  in override_max_clk_values()
2428 		curr_clk_limit->dcfclk_mhz = max_clk_limit->dcfclk_mhz;  in override_max_clk_values()
2469 		if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz)  in build_synthetic_soc_states()
2470 			max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;  in build_synthetic_soc_states()
2494 		if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) {  in build_synthetic_soc_states()
2496 			if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz)  in build_synthetic_soc_states()
2514 	if (!max_clk_data.dcfclk_mhz || !max_clk_data.dispclk_mhz || !max_clk_data.dtbclk_mhz)  in build_synthetic_soc_states()
2521 		max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz *  in build_synthetic_soc_states()
2539 		entry.dcfclk_mhz = dcfclk_sta_targets[i];  in build_synthetic_soc_states()
2549 	entry.dcfclk_mhz = max_clk_data.dcfclk_mhz;  in build_synthetic_soc_states()
2559 		entry.dcfclk_mhz = 0;  in build_synthetic_soc_states()
2571 			entry.dcfclk_mhz = 0;  in build_synthetic_soc_states()
2582 		entry.dcfclk_mhz = 0;  in build_synthetic_soc_states()
2597 		if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz ||  in build_synthetic_soc_states()
2607 		max_dc_limits_entry.dcfclk_mhz = max_clk_data.dcfclk_mhz;  in build_synthetic_soc_states()
2655 		if (table[i].dcfclk_mhz < min_dcfclk_mhz) {  in build_synthetic_soc_states()
2656 			table[i].dcfclk_mhz = min_dcfclk_mhz;  in build_synthetic_soc_states()
2663 		if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&  in build_synthetic_soc_states()
2787 			unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};  in dcn32_update_bw_bounding_box_fpu()  local
2799 				if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)  in dcn32_update_bw_bounding_box_fpu()
2800 					max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;  in dcn32_update_bw_bounding_box_fpu()
2801 				if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 &&  in dcn32_update_bw_bounding_box_fpu()
2802 						bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk)  in dcn32_update_bw_bounding_box_fpu()
2803 					min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz;  in dcn32_update_bw_bounding_box_fpu()
2814 				max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;  in dcn32_update_bw_bounding_box_fpu()
2844 				if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {  in dcn32_update_bw_bounding_box_fpu()
2845 					optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;  in dcn32_update_bw_bounding_box_fpu()
2865 					dcfclk_mhz[num_states] = dcfclk_sta_targets[i];  in dcn32_update_bw_bounding_box_fpu()
2869 						dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];  in dcn32_update_bw_bounding_box_fpu()
2878 				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];  in dcn32_update_bw_bounding_box_fpu()
2884 				dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];  in dcn32_update_bw_bounding_box_fpu()
2891 				dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];  in dcn32_update_bw_bounding_box_fpu()
2892 				dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];  in dcn32_update_bw_bounding_box_fpu()
3136 	dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0;  in dcn32_set_clock_limits()