| /openbmc/qemu/hw/pci-bridge/ |
| H A D | cxl_upstream.c | 36 return &usp->cxl_cstate; in cxl_usp_to_cstate()
46 addr -= usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob; in cxl_usp_dvsec_write_config()
140 CDATObject *cdat = &CXL_USP(doe_cap->pdev)->cxl_cstate.cdat; in cxl_doe_cdat_rsp()
300 CXLComponentState *cxl_cstate = &usp->cxl_cstate; in cxl_usp_realize() local
301 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_usp_realize()
331 cxl_cstate->dvsec_offset = CXL_UPSTREAM_PORT_DVSEC_OFFSET; in cxl_usp_realize()
332 cxl_cstate->pdev = d; in cxl_usp_realize()
333 build_dvsecs(cxl_cstate); in cxl_usp_realize()
343 cxl_cstate->cdat.build_cdat_table = build_cdat_table; in cxl_usp_realize()
345 cxl_cstate->cdat.private = d; in cxl_usp_realize()
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| H A D | cxl_downstream.c | 24 CXLComponentState cxl_cstate; member
36 uint32_t *reg_state = dsp->cxl_cstate.crb.cache_mem_registers; in latch_registers()
37 uint32_t *write_msk = dsp->cxl_cstate.crb.cache_mem_regs_write_mask; in latch_registers()
48 CXLComponentState *cxl_cstate = &dsp->cxl_cstate; in cxl_dsp_dvsec_write_config() local
50 if (range_contains(&cxl_cstate->dvsecs[EXTENSIONS_PORT_DVSEC], addr)) { in cxl_dsp_dvsec_write_config()
52 addr -= cxl_cstate->dvsecs[EXTENSIONS_PORT_DVSEC].lob; in cxl_dsp_dvsec_write_config()
140 CXLComponentState *cxl_cstate = &dsp->cxl_cstate; in cxl_dsp_realize() local
141 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_dsp_realize()
181 cxl_cstate->dvsec_offset = CXL_DOWNSTREAM_PORT_DVSEC_OFFSET; in cxl_dsp_realize()
182 cxl_cstate->pdev = d; in cxl_dsp_realize()
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| H A D | cxl_root_port.c | 48 CXLComponentState cxl_cstate; member
100 uint32_t *reg_state = crp->cxl_cstate.crb.cache_mem_registers; in latch_registers()
101 uint32_t *write_msk = crp->cxl_cstate.crb.cache_mem_regs_write_mask; in latch_registers()
151 CXLComponentState *cxl_cstate = &crp->cxl_cstate; in cxl_rp_realize() local
152 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_rp_realize()
176 cxl_cstate->dvsec_offset = CXL_ROOT_PORT_DVSEC_OFFSET; in cxl_rp_realize()
177 cxl_cstate->pdev = pci_dev; in cxl_rp_realize()
178 build_dvsecs(&crp->cxl_cstate); in cxl_rp_realize()
180 cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate, in cxl_rp_realize()
217 if (range_contains(&crp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], addr)) { in cxl_rp_dvsec_write_config()
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| H A D | pci_expander_bridge.c | 64 return &host->cxl_cstate;
183 CXLComponentState *cxl_cstate = &cxl->cxl_cstate; in pxb_cxl_realize() local
184 struct MemoryRegion *mr = &cxl_cstate->crb.component_registers; in pxb_cxl_realize()
186 cxl_component_register_block_init(OBJECT(dev), cxl_cstate, in pxb_cxl_realize()
201 CXLComponentState *cxl_cstate = &cxl->cxl_cstate; in pxb_cxl_hook_up_registers() local
202 struct MemoryRegion *mr = &cxl_cstate->crb.component_registers; in pxb_cxl_hook_up_registers()
287 CXLComponentState *cxl_cstate = &cxl->cxl_cstate; in pxb_cxl_dev_reset() local
289 uint32_t *reg_state = cxl_cstate->crb.cache_mem_registers; in pxb_cxl_dev_reset()
290 uint32_t *write_msk = cxl_cstate->crb.cache_mem_regs_write_mask; in pxb_cxl_dev_reset()
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| /openbmc/qemu/hw/cxl/ |
| H A D | switch-mailbox-cci.c | 29 CXLComponentState *cxl_cstate = &cswmb->cxl_cstate; in cswbcci_realize() local
41 cxl_cstate->dvsec_offset = 0x100; in cswbcci_realize()
42 cxl_cstate->pdev = pci_dev; in cswbcci_realize()
54 cxl_component_create_dvsec(cxl_cstate, CXL3_SWITCH_MAILBOX_CCI, in cswbcci_realize()
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| H A D | cxl-component-utils.c | 67 CXLComponentState *cxl_cstate = opaque; in cxl_cache_mem_read_reg() local
68 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_cache_mem_read_reg()
73 return cregs->special_ops->read(cxl_cstate, offset, 4); in cxl_cache_mem_read_reg()
91 static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset, in dumb_hdm_handler() argument
94 ComponentRegisters *cregs = &cxl_cstate->crb; in dumb_hdm_handler()
124 CXLComponentState *cxl_cstate = opaque; in cxl_cache_mem_write_reg() local
125 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_cache_mem_write_reg()
137 cregs->special_ops->write(cxl_cstate, offset, value, size); in cxl_cache_mem_write_reg()
143 dumb_hdm_handler(cxl_cstate, offset, value); in cxl_cache_mem_write_reg()
191 CXLComponentState *cxl_cstate, in cxl_component_register_block_init() argument
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| H A D | cxl-cdat.c | 190 void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp) in cxl_doe_cdat_init() argument
192 CDATObject *cdat = &cxl_cstate->cdat; in cxl_doe_cdat_init()
201 void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp) in cxl_doe_cdat_update() argument
203 CDATObject *cdat = &cxl_cstate->cdat; in cxl_doe_cdat_update()
210 void cxl_doe_cdat_release(CXLComponentState *cxl_cstate) in cxl_doe_cdat_release() argument
212 CDATObject *cdat = &cxl_cstate->cdat; in cxl_doe_cdat_release()
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| /openbmc/qemu/hw/mem/ |
| H A D | cxl_type3.c | 315 CXLComponentState *cxl_cstate = &ct3d->cxl_cstate; in build_dvsecs() local
482 CXLComponentState *cxl_cstate = opaque; in ct3d_reg_write() local
484 CXLType3Dev *ct3d = container_of(cxl_cstate, CXLType3Dev, cxl_cstate); in ct3d_reg_write()
684 CXLComponentState *cxl_cstate = &ct3d->cxl_cstate; in ct3_realize() local
704 cxl_cstate->dvsec_offset = 0x100; in ct3_realize()
707 ct3d->cxl_cstate.pdev = pci_dev; in ct3_realize()
741 cxl_cstate->cdat.private = ct3d; in ct3_realize()
742 cxl_doe_cdat_init(cxl_cstate, errp); in ct3_realize()
758 cxl_doe_cdat_release(cxl_cstate); in ct3_realize()
774 CXLComponentState *cxl_cstate = &ct3d->cxl_cstate; in ct3_exit() local
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| /openbmc/qemu/include/hw/cxl/ |
| H A D | cxl_component.h | 230 CXLComponentState *cxl_cstate,
236 void cxl_component_create_dvsec(CXLComponentState *cxl_cstate,
252 void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp);
253 void cxl_doe_cdat_release(CXLComponentState *cxl_cstate);
254 void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp);
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| H A D | cxl.h | 52 CXLComponentState cxl_cstate; member
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| H A D | cxl_device.h | 408 CXLComponentState cxl_cstate; member
449 CXLComponentState cxl_cstate; member
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| /openbmc/qemu/include/hw/pci-bridge/ |
| H A D | cxl_upstream_port.h | 13 CXLComponentState cxl_cstate; member
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