| /openbmc/u-boot/board/compulab/common/ |
| H A D | omap3_smc911x.c | 32 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; in cl_omap3_smc911x_setup_net_chip_gmpc() local
38 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in cl_omap3_smc911x_setup_net_chip_gmpc()
41 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in cl_omap3_smc911x_setup_net_chip_gmpc()
44 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in cl_omap3_smc911x_setup_net_chip_gmpc()
45 &ctrl_base->gpmc_nadv_ale); in cl_omap3_smc911x_setup_net_chip_gmpc()
|
| /openbmc/u-boot/drivers/misc/ |
| H A D | aspeed-fsi.c | 88 static const u32 ctrl_base = 0x80000000; variable
258 opb_read(aspeed, ctrl_base + FSI_MRESP0, 4, &mresp0); in check_errors()
259 opb_read(aspeed, ctrl_base + FSI_MSTAP0, 4, &mstap0); in check_errors()
260 opb_read(aspeed, ctrl_base + FSI_MESRB0, 4, &mesrb0); in check_errors()
272 ret = opb_write(aspeed, ctrl_base + 0xd0, in check_errors()
328 result = opb_write(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), in aspeed_fsi_link_enable()
333 ret = opb_read(aspeed, ctrl_base + FSI_MENP0 + (4 * idx), in aspeed_fsi_link_enable()
370 opb_read(aspeed, ctrl_base + FSI_MMODE, 4, &mmode); in aspeed_fsi_status()
371 opb_read(aspeed, ctrl_base + FSI_MRESP0, 4, &mresp0); in aspeed_fsi_status()
372 opb_read(aspeed, ctrl_base + FSI_MSTAP0, 4, &mstap0); in aspeed_fsi_status()
[all …]
|
| H A D | aspeed_dp.c | 38 void *ctrl_base; member
88 dp->ctrl_base = (void *)devfdt_get_addr_index(dev, 0); in aspeed_dp_probe()
114 writel(readl(dp->ctrl_base + 0xB8) & ~(BIT(24) | BIT(28)), dp->ctrl_base + 0xB8); in aspeed_dp_probe()
160 dp->ctrl_base = (void *)devfdt_get_addr_index(dev, 0); in dp_aspeed_ofdata_to_platdata()
|
| /openbmc/u-boot/drivers/pci/ |
| H A D | pcie_dw_mvebu.c | 109 void *ctrl_base; member
146 pcie->ctrl_base + PCIE_ATU_VIEWPORT); in pcie_dw_prog_outbound_atu()
147 writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE); in pcie_dw_prog_outbound_atu()
148 writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE); in pcie_dw_prog_outbound_atu()
150 pcie->ctrl_base + PCIE_ATU_LIMIT); in pcie_dw_prog_outbound_atu()
152 pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); in pcie_dw_prog_outbound_atu()
154 pcie->ctrl_base + PCIE_ATU_UPPER_TARGET); in pcie_dw_prog_outbound_atu()
155 writel(type, pcie->ctrl_base + PCIE_ATU_CR1); in pcie_dw_prog_outbound_atu()
156 writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2); in pcie_dw_prog_outbound_atu()
194 va_address = (uintptr_t)pcie->ctrl_base; in set_cfg_address()
[all …]
|
| /openbmc/u-boot/board/isee/igep00x0/ |
| H A D | igep00x0.c | 106 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; in setup_net_chip() local
120 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in setup_net_chip()
122 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in setup_net_chip()
124 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in setup_net_chip()
125 &ctrl_base->gpmc_nadv_ale); in setup_net_chip()
|
| /openbmc/u-boot/board/ti/evm/ |
| H A D | evm.c | 236 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; in setup_net_chip() local
248 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in setup_net_chip()
250 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in setup_net_chip()
252 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in setup_net_chip()
253 &ctrl_base->gpmc_nadv_ale); in setup_net_chip()
|
| /openbmc/u-boot/board/overo/ |
| H A D | overo.c | 315 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; in setup_net_chip() local
318 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in setup_net_chip()
320 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in setup_net_chip()
322 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in setup_net_chip()
323 &ctrl_base->gpmc_nadv_ale); in setup_net_chip()
|
| /openbmc/qemu/hw/arm/ |
| H A D | bcm2838.c | 85 sysbus_mmio_map(SYS_BUS_DEVICE(&s_base->control), 0, bc_base->ctrl_base); in bcm2838_realize()
132 bc_base->ctrl_base + BCM2838_GIC_BASE + GIC_DIST_OFS); in bcm2838_realize()
134 bc_base->ctrl_base + BCM2838_GIC_BASE + GIC_CPU_OFS); in bcm2838_realize()
136 bc_base->ctrl_base + BCM2838_GIC_BASE + GIC_VIFACE_THIS_OFS); in bcm2838_realize()
138 bc_base->ctrl_base + BCM2838_GIC_BASE + GIC_VCPU_OFS); in bcm2838_realize()
142 bc_base->ctrl_base + BCM2838_GIC_BASE in bcm2838_realize()
244 bc_base->ctrl_base = 0xff800000; in bcm2838_class_init()
|
| H A D | bcm2836.c | 39 if (bc->ctrl_base) { in bcm283x_base_init()
124 sysbus_mmio_map(SYS_BUS_DEVICE(&s_base->control), 0, bc->ctrl_base); in bcm2836_realize()
193 bc->ctrl_base = 0x40000000; in bcm2836_class_init()
207 bc->ctrl_base = 0x40000000; in bcm2837_class_init()
|
| /openbmc/u-boot/arch/arm/mach-omap2/omap3/ |
| H A D | boot.c | 47 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; in omap_sys_boot_device() local
51 sys_boot = readl(&ctrl_base->status) & ((1 << 5) - 1); in omap_sys_boot_device()
|
| H A D | sys_info.c | 25 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; variable
60 return readl(&ctrl_base->ctrl_omap_stat); in get_cpu_type()
236 return (readl(&ctrl_base->status) & SYSBOOT_MASK); in get_boot_type()
|
| /openbmc/qemu/include/hw/arm/ |
| H A D | bcm2836.h | 56 hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ member
|
| /openbmc/u-boot/drivers/usb/musb-new/ |
| H A D | am35x.c | 94 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_enable()
118 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_disable()
171 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG, in otg_timer()
226 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_interrupt()
381 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_init()
|
| H A D | musb_dsps.c | 158 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_enable()
188 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_disable()
235 dsps_writel(musb->ctrl_base, wrp->coreintr_set, in otg_timer()
295 void __iomem *reg_base = musb->ctrl_base; in dsps_interrupt()
422 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_init()
461 dsps_writel(musb->ctrl_base, wrp->phy_utmi, val); in dsps_musb_init()
|
| H A D | musb_core.h | 355 void __iomem *ctrl_base; member
|
| H A D | musb_core.c | 1859 musb->ctrl_base = mbase; in allocate_instance()
2203 void __iomem *ctrl_base = musb->ctrl_base; in musb_remove() local
2214 iounmap(ctrl_base); in musb_remove()
|