| /openbmc/u-boot/drivers/spi/ |
| H A D | ich.c | 85 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) in ich_set_bbar() argument
91 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; in ich_set_bbar()
93 ich_writel(ctlr, ichspi_bbar, ctlr->bbar); in ich_set_bbar()
115 struct ich_spi_priv *ctlr) in ich_init_controller() argument
128 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); in ich_init_controller()
129 ctlr->menubytes = sizeof(ich7_spi->opmenu); in ich_init_controller()
130 ctlr->optype = offsetof(struct ich7_spi_regs, optype); in ich_init_controller()
131 ctlr->addr = offsetof(struct ich7_spi_regs, spia); in ich_init_controller()
132 ctlr->data = offsetof(struct ich7_spi_regs, spid); in ich_init_controller()
133 ctlr->databytes = sizeof(ich7_spi->spid); in ich_init_controller()
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| H A D | spi-mem.c | 36 int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, in spi_controller_dma_map_mem_op_data() argument
45 if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx) in spi_controller_dma_map_mem_op_data()
46 dmadev = ctlr->dma_tx->device->dev; in spi_controller_dma_map_mem_op_data()
47 else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx) in spi_controller_dma_map_mem_op_data()
48 dmadev = ctlr->dma_rx->device->dev; in spi_controller_dma_map_mem_op_data()
50 dmadev = ctlr->dev.parent; in spi_controller_dma_map_mem_op_data()
55 return spi_map_buf(ctlr, dmadev, sgt, op->data.buf.in, op->data.nbytes, in spi_controller_dma_map_mem_op_data()
82 void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, in spi_controller_dma_unmap_mem_op_data() argument
91 if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx) in spi_controller_dma_unmap_mem_op_data()
92 dmadev = ctlr->dma_tx->device->dev; in spi_controller_dma_unmap_mem_op_data()
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| /openbmc/qemu/tests/qtest/ |
| H A D | pnv-host-i2c-test.c | 39 PnvI2cCtlr *ctlr; member
45 static uint64_t pnv_i2c_xscom_addr(PnvI2cCtlr *ctlr, uint32_t reg) in pnv_i2c_xscom_addr() argument
47 return pnv_xscom_addr(ctlr->chip, PNV10_XSCOM_I2CM_BASE + in pnv_i2c_xscom_addr()
48 (PNV10_XSCOM_I2CM_SIZE * ctlr->engine) + reg); in pnv_i2c_xscom_addr()
51 static uint64_t pnv_i2c_xscom_read(PnvI2cCtlr *ctlr, uint32_t reg) in pnv_i2c_xscom_read() argument
53 return qtest_readq(ctlr->qts, pnv_i2c_xscom_addr(ctlr, reg)); in pnv_i2c_xscom_read()
56 static void pnv_i2c_xscom_write(PnvI2cCtlr *ctlr, uint32_t reg, uint64_t val) in pnv_i2c_xscom_write() argument
58 qtest_writeq(ctlr->qts, pnv_i2c_xscom_addr(ctlr, reg), val); in pnv_i2c_xscom_write()
70 pnv_i2c_xscom_write(dev->ctlr, I2C_MODE_REG, reg64); in pnv_i2c_send()
73 reg64 = pnv_i2c_xscom_read(dev->ctlr, I2C_EXTD_STAT_REG); in pnv_i2c_send()
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| /openbmc/u-boot/drivers/gpio/ |
| H A D | tegra_gpio.c | 45 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; in get_config() local
46 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in get_config()
62 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; in set_config() local
63 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in set_config()
80 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; in get_direction() local
81 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in get_direction()
97 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; in set_direction() local
98 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in set_direction()
115 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; in set_level() local
116 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in set_level()
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| H A D | sunxi_gpio.c | 289 struct sunxi_gpio_reg *ctlr; in gpio_sunxi_bind() local
296 ctlr = (struct sunxi_gpio_reg *)devfdt_get_addr(parent); in gpio_sunxi_bind()
304 plat->regs = &ctlr->gpio_bank[bank]; in gpio_sunxi_bind()
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| /openbmc/u-boot/drivers/pci/ |
| H A D | pci_auto.c | 171 struct udevice *ctlr = pci_get_controller(dev); in dm_pciauto_prescan_setup_bridge() local
172 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); in dm_pciauto_prescan_setup_bridge()
184 PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq); in dm_pciauto_prescan_setup_bridge()
185 dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq); in dm_pciauto_prescan_setup_bridge()
252 struct udevice *ctlr = pci_get_controller(dev); in dm_pciauto_postscan_setup_bridge() local
253 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); in dm_pciauto_postscan_setup_bridge()
261 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq); in dm_pciauto_postscan_setup_bridge()
319 struct udevice *ctlr = pci_get_controller(dev); in dm_pciauto_config_device() local
320 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); in dm_pciauto_config_device()
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| H A D | pci-uclass.c | 956 hose->ctlr = bus; in pci_uclass_pre_probe()
962 hose->ctlr = parent_hose->bus; in pci_uclass_pre_probe()
1050 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size); in pci_bridge_read_config()
1059 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size); in pci_bridge_write_config()
1212 static int _dm_pci_bus_to_phys(struct udevice *ctlr, in _dm_pci_bus_to_phys() argument
1216 struct pci_controller *hose = dev_get_uclass_priv(ctlr); in _dm_pci_bus_to_phys()
1248 struct udevice *ctlr; in dm_pci_bus_to_phys() local
1252 ctlr = pci_get_controller(dev); in dm_pci_bus_to_phys()
1259 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, in dm_pci_bus_to_phys()
1266 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr); in dm_pci_bus_to_phys()
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| H A D | pcie_dw_mvebu.c | 477 struct udevice *ctlr = pci_get_controller(dev); in pcie_dw_mvebu_probe() local
478 struct pci_controller *hose = dev_get_uclass_priv(ctlr); in pcie_dw_mvebu_probe()
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| H A D | pci_mvebu.c | 278 struct udevice *ctlr = pci_get_controller(dev); in mvebu_pcie_probe() local
279 struct pci_controller *hose = dev_get_uclass_priv(ctlr); in mvebu_pcie_probe()
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| /openbmc/u-boot/include/ |
| H A D | spi-mem.h | 213 int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
217 void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
222 spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, in spi_controller_dma_map_mem_op_data() argument
230 spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, in spi_controller_dma_unmap_mem_op_data() argument
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| H A D | pci.h | 560 struct udevice *ctlr; member
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| /openbmc/qemu/hw/intc/ |
| H A D | arm_gicv3_its_kvm.c | 147 GITS_CTLR, &s->ctlr, false, &error_abort); in kvm_arm_its_pre_save()
197 GITS_CTLR, &s->ctlr, true, &error_abort); in kvm_arm_its_post_load()
225 GITS_CTLR, &s->ctlr, true, &error_abort); in kvm_arm_its_reset_hold()
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| H A D | arm_gicv3_its_common.c | 58 VMSTATE_UINT32(ctlr, GICv3ITSState),
130 s->ctlr = 0; in gicv3_its_common_reset_hold()
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| H A D | arm_gicv3_its.c | 1255 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { in process_cmdq()
1563 if (s->ctlr & R_GITS_CTLR_ENABLED_MASK) { in gicv3_its_translation_write()
1587 s->ctlr |= R_GITS_CTLR_ENABLED_MASK; in its_writel()
1592 s->ctlr &= ~R_GITS_CTLR_ENABLED_MASK; in its_writel()
1600 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { in its_writel()
1610 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { in its_writel()
1651 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { in its_writel()
1692 *data = s->ctlr; in its_readl()
1752 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { in its_writell()
1767 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { in its_writell()
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| H A D | arm_gic.c | 147 if (!virt && !(s->ctlr & group_mask)) { in gic_irq_signaling_enabled()
963 return extract32(s->ctlr, 1, 1); in gic_dist_readb()
965 return s->ctlr; in gic_dist_readb()
1204 s->ctlr = deposit32(s->ctlr, 1, 1, value); in gic_dist_writeb()
1206 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); in gic_dist_writeb()
1208 s->ctlr = value & GICD_CTLR_EN_GRP0; in gic_dist_writeb()
1211 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", in gic_dist_writeb()
1212 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); in gic_dist_writeb()
1893 uint32_t ctlr; in gic_vmcr_write() local
1898 ctlr = FIELD_EX32(value, GICH_VMCR, VMCCtlr); in gic_vmcr_write()
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| H A D | arm_gic_common.c | 108 VMSTATE_UINT32(ctlr, GICState),
331 s->ctlr = 0; in arm_gic_common_reset_hold()
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| H A D | arm_gic_kvm.c | 305 reg = s->ctlr; in kvm_arm_gic_put()
401 s->ctlr = reg; in kvm_arm_gic_get()
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| /openbmc/qemu/docs/specs/ |
| H A D | index.rst | 34 virt-ctlr
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| /openbmc/qemu/include/hw/intc/ |
| H A D | arm_gicv3_its_common.h | 71 uint32_t ctlr; member
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| H A D | arm_gic_common.h | 81 uint32_t ctlr; member
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