1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
21853030eSSimon Glass /*
31853030eSSimon Glass * Copyright (c) 2011-12 The Chromium OS Authors.
41853030eSSimon Glass *
51853030eSSimon Glass * This file is derived from the flashrom project.
61853030eSSimon Glass */
79eb4339bSBin Meng
81853030eSSimon Glass #include <common.h>
9ba457562SSimon Glass #include <dm.h>
105093badbSSimon Glass #include <errno.h>
111853030eSSimon Glass #include <malloc.h>
12f2b85ab5SSimon Glass #include <pch.h>
131853030eSSimon Glass #include <pci.h>
141853030eSSimon Glass #include <pci_ids.h>
15f2b85ab5SSimon Glass #include <spi.h>
161853030eSSimon Glass #include <asm/io.h>
171853030eSSimon Glass
181853030eSSimon Glass #include "ich.h"
191853030eSSimon Glass
201f9eb59dSBin Meng DECLARE_GLOBAL_DATA_PTR;
211f9eb59dSBin Meng
22fffe25dbSSimon Glass #ifdef DEBUG_TRACE
23fffe25dbSSimon Glass #define debug_trace(fmt, args...) debug(fmt, ##args)
24fffe25dbSSimon Glass #else
25fffe25dbSSimon Glass #define debug_trace(x, args...)
26fffe25dbSSimon Glass #endif
27fffe25dbSSimon Glass
ich_readb(struct ich_spi_priv * priv,int reg)28ba457562SSimon Glass static u8 ich_readb(struct ich_spi_priv *priv, int reg)
291853030eSSimon Glass {
30ba457562SSimon Glass u8 value = readb(priv->base + reg);
311853030eSSimon Glass
32fffe25dbSSimon Glass debug_trace("read %2.2x from %4.4x\n", value, reg);
331853030eSSimon Glass
341853030eSSimon Glass return value;
351853030eSSimon Glass }
361853030eSSimon Glass
ich_readw(struct ich_spi_priv * priv,int reg)37ba457562SSimon Glass static u16 ich_readw(struct ich_spi_priv *priv, int reg)
381853030eSSimon Glass {
39ba457562SSimon Glass u16 value = readw(priv->base + reg);
401853030eSSimon Glass
41fffe25dbSSimon Glass debug_trace("read %4.4x from %4.4x\n", value, reg);
421853030eSSimon Glass
431853030eSSimon Glass return value;
441853030eSSimon Glass }
451853030eSSimon Glass
ich_readl(struct ich_spi_priv * priv,int reg)46ba457562SSimon Glass static u32 ich_readl(struct ich_spi_priv *priv, int reg)
471853030eSSimon Glass {
48ba457562SSimon Glass u32 value = readl(priv->base + reg);
491853030eSSimon Glass
50fffe25dbSSimon Glass debug_trace("read %8.8x from %4.4x\n", value, reg);
511853030eSSimon Glass
521853030eSSimon Glass return value;
531853030eSSimon Glass }
541853030eSSimon Glass
ich_writeb(struct ich_spi_priv * priv,u8 value,int reg)55ba457562SSimon Glass static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
561853030eSSimon Glass {
57ba457562SSimon Glass writeb(value, priv->base + reg);
58fffe25dbSSimon Glass debug_trace("wrote %2.2x to %4.4x\n", value, reg);
591853030eSSimon Glass }
601853030eSSimon Glass
ich_writew(struct ich_spi_priv * priv,u16 value,int reg)61ba457562SSimon Glass static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
621853030eSSimon Glass {
63ba457562SSimon Glass writew(value, priv->base + reg);
64fffe25dbSSimon Glass debug_trace("wrote %4.4x to %4.4x\n", value, reg);
651853030eSSimon Glass }
661853030eSSimon Glass
ich_writel(struct ich_spi_priv * priv,u32 value,int reg)67ba457562SSimon Glass static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
681853030eSSimon Glass {
69ba457562SSimon Glass writel(value, priv->base + reg);
70fffe25dbSSimon Glass debug_trace("wrote %8.8x to %4.4x\n", value, reg);
711853030eSSimon Glass }
721853030eSSimon Glass
write_reg(struct ich_spi_priv * priv,const void * value,int dest_reg,uint32_t size)73ba457562SSimon Glass static void write_reg(struct ich_spi_priv *priv, const void *value,
74ba457562SSimon Glass int dest_reg, uint32_t size)
751853030eSSimon Glass {
76ba457562SSimon Glass memcpy_toio(priv->base + dest_reg, value, size);
771853030eSSimon Glass }
781853030eSSimon Glass
read_reg(struct ich_spi_priv * priv,int src_reg,void * value,uint32_t size)79ba457562SSimon Glass static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
80ba457562SSimon Glass uint32_t size)
811853030eSSimon Glass {
82ba457562SSimon Glass memcpy_fromio(value, priv->base + src_reg, size);
831853030eSSimon Glass }
841853030eSSimon Glass
ich_set_bbar(struct ich_spi_priv * ctlr,uint32_t minaddr)85ba457562SSimon Glass static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
861853030eSSimon Glass {
871853030eSSimon Glass const uint32_t bbar_mask = 0x00ffff00;
881853030eSSimon Glass uint32_t ichspi_bbar;
891853030eSSimon Glass
901853030eSSimon Glass minaddr &= bbar_mask;
91ba457562SSimon Glass ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
921853030eSSimon Glass ichspi_bbar |= minaddr;
93ba457562SSimon Glass ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
941853030eSSimon Glass }
951853030eSSimon Glass
961853030eSSimon Glass /* @return 1 if the SPI flash supports the 33MHz speed */
ich9_can_do_33mhz(struct udevice * dev)97f2b85ab5SSimon Glass static int ich9_can_do_33mhz(struct udevice *dev)
981853030eSSimon Glass {
991853030eSSimon Glass u32 fdod, speed;
1001853030eSSimon Glass
1011853030eSSimon Glass /* Observe SPI Descriptor Component Section 0 */
102f2b85ab5SSimon Glass dm_pci_write_config32(dev->parent, 0xb0, 0x1000);
1031853030eSSimon Glass
1041853030eSSimon Glass /* Extract the Write/Erase SPI Frequency from descriptor */
105f2b85ab5SSimon Glass dm_pci_read_config32(dev->parent, 0xb4, &fdod);
1061853030eSSimon Glass
1071853030eSSimon Glass /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
1081853030eSSimon Glass speed = (fdod >> 21) & 7;
1091853030eSSimon Glass
1101853030eSSimon Glass return speed == 1;
1111853030eSSimon Glass }
1121853030eSSimon Glass
ich_init_controller(struct udevice * dev,struct ich_spi_platdata * plat,struct ich_spi_priv * ctlr)113f2b85ab5SSimon Glass static int ich_init_controller(struct udevice *dev,
114f2b85ab5SSimon Glass struct ich_spi_platdata *plat,
115ba457562SSimon Glass struct ich_spi_priv *ctlr)
1161853030eSSimon Glass {
117f2b85ab5SSimon Glass ulong sbase_addr;
118f2b85ab5SSimon Glass void *sbase;
1195093badbSSimon Glass
1205093badbSSimon Glass /* SBASE is similar */
1213e389d8bSBin Meng pch_get_spi_base(dev->parent, &sbase_addr);
122f2b85ab5SSimon Glass sbase = (void *)sbase_addr;
123f2b85ab5SSimon Glass debug("%s: sbase=%p\n", __func__, sbase);
1245093badbSSimon Glass
1256e670b5cSBin Meng if (plat->ich_version == ICHV_7) {
126f2b85ab5SSimon Glass struct ich7_spi_regs *ich7_spi = sbase;
1271853030eSSimon Glass
128ba457562SSimon Glass ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
1291853030eSSimon Glass ctlr->menubytes = sizeof(ich7_spi->opmenu);
130ba457562SSimon Glass ctlr->optype = offsetof(struct ich7_spi_regs, optype);
131ba457562SSimon Glass ctlr->addr = offsetof(struct ich7_spi_regs, spia);
132ba457562SSimon Glass ctlr->data = offsetof(struct ich7_spi_regs, spid);
1331853030eSSimon Glass ctlr->databytes = sizeof(ich7_spi->spid);
134ba457562SSimon Glass ctlr->status = offsetof(struct ich7_spi_regs, spis);
135ba457562SSimon Glass ctlr->control = offsetof(struct ich7_spi_regs, spic);
136ba457562SSimon Glass ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
137ba457562SSimon Glass ctlr->preop = offsetof(struct ich7_spi_regs, preop);
1381853030eSSimon Glass ctlr->base = ich7_spi;
1396e670b5cSBin Meng } else if (plat->ich_version == ICHV_9) {
140f2b85ab5SSimon Glass struct ich9_spi_regs *ich9_spi = sbase;
1411853030eSSimon Glass
142ba457562SSimon Glass ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
1431853030eSSimon Glass ctlr->menubytes = sizeof(ich9_spi->opmenu);
144ba457562SSimon Glass ctlr->optype = offsetof(struct ich9_spi_regs, optype);
145ba457562SSimon Glass ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
146ba457562SSimon Glass ctlr->data = offsetof(struct ich9_spi_regs, fdata);
1471853030eSSimon Glass ctlr->databytes = sizeof(ich9_spi->fdata);
148ba457562SSimon Glass ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
149ba457562SSimon Glass ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
150ba457562SSimon Glass ctlr->speed = ctlr->control + 2;
151ba457562SSimon Glass ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
152ba457562SSimon Glass ctlr->preop = offsetof(struct ich9_spi_regs, preop);
15350787928SSimon Glass ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
1541853030eSSimon Glass ctlr->pr = &ich9_spi->pr[0];
1551853030eSSimon Glass ctlr->base = ich9_spi;
1561853030eSSimon Glass } else {
157ba457562SSimon Glass debug("ICH SPI: Unrecognised ICH version %d\n",
158ba457562SSimon Glass plat->ich_version);
159ba457562SSimon Glass return -EINVAL;
1601853030eSSimon Glass }
1611853030eSSimon Glass
1621853030eSSimon Glass /* Work out the maximum speed we can support */
1631853030eSSimon Glass ctlr->max_speed = 20000000;
1646e670b5cSBin Meng if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
1651853030eSSimon Glass ctlr->max_speed = 33000000;
166f2b85ab5SSimon Glass debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
167ba457562SSimon Glass plat->ich_version, ctlr->base, ctlr->max_speed);
1681853030eSSimon Glass
1691853030eSSimon Glass ich_set_bbar(ctlr, 0);
1701853030eSSimon Glass
1711853030eSSimon Glass return 0;
1721853030eSSimon Glass }
1731853030eSSimon Glass
spi_use_out(struct spi_trans * trans,unsigned bytes)1741853030eSSimon Glass static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
1751853030eSSimon Glass {
1761853030eSSimon Glass trans->out += bytes;
1771853030eSSimon Glass trans->bytesout -= bytes;
1781853030eSSimon Glass }
1791853030eSSimon Glass
spi_use_in(struct spi_trans * trans,unsigned bytes)1801853030eSSimon Glass static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
1811853030eSSimon Glass {
1821853030eSSimon Glass trans->in += bytes;
1831853030eSSimon Glass trans->bytesin -= bytes;
1841853030eSSimon Glass }
1851853030eSSimon Glass
spi_lock_down(struct ich_spi_platdata * plat,void * sbase)186ab201074SBin Meng static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
187ab201074SBin Meng {
188ab201074SBin Meng if (plat->ich_version == ICHV_7) {
189ab201074SBin Meng struct ich7_spi_regs *ich7_spi = sbase;
190ab201074SBin Meng
191ab201074SBin Meng setbits_le16(&ich7_spi->spis, SPIS_LOCK);
192ab201074SBin Meng } else if (plat->ich_version == ICHV_9) {
193ab201074SBin Meng struct ich9_spi_regs *ich9_spi = sbase;
194ab201074SBin Meng
195ab201074SBin Meng setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
196ab201074SBin Meng }
197ab201074SBin Meng }
198ab201074SBin Meng
spi_lock_status(struct ich_spi_platdata * plat,void * sbase)1993e791416SBin Meng static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
2003e791416SBin Meng {
2013e791416SBin Meng int lock = 0;
2023e791416SBin Meng
2033e791416SBin Meng if (plat->ich_version == ICHV_7) {
2043e791416SBin Meng struct ich7_spi_regs *ich7_spi = sbase;
2053e791416SBin Meng
2063e791416SBin Meng lock = readw(&ich7_spi->spis) & SPIS_LOCK;
2073e791416SBin Meng } else if (plat->ich_version == ICHV_9) {
2083e791416SBin Meng struct ich9_spi_regs *ich9_spi = sbase;
2093e791416SBin Meng
2103e791416SBin Meng lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
2113e791416SBin Meng }
2123e791416SBin Meng
2133e791416SBin Meng return lock != 0;
2143e791416SBin Meng }
2153e791416SBin Meng
spi_setup_type(struct spi_trans * trans,int data_bytes)2161853030eSSimon Glass static void spi_setup_type(struct spi_trans *trans, int data_bytes)
2171853030eSSimon Glass {
2181853030eSSimon Glass trans->type = 0xFF;
2191853030eSSimon Glass
2209eb4339bSBin Meng /* Try to guess spi type from read/write sizes */
2211853030eSSimon Glass if (trans->bytesin == 0) {
2221853030eSSimon Glass if (trans->bytesout + data_bytes > 4)
2231853030eSSimon Glass /*
2241853030eSSimon Glass * If bytesin = 0 and bytesout > 4, we presume this is
2251853030eSSimon Glass * a write data operation, which is accompanied by an
2261853030eSSimon Glass * address.
2271853030eSSimon Glass */
2281853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
2291853030eSSimon Glass else
2301853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
2311853030eSSimon Glass return;
2321853030eSSimon Glass }
2331853030eSSimon Glass
2341853030eSSimon Glass if (trans->bytesout == 1) { /* and bytesin is > 0 */
2351853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
2361853030eSSimon Glass return;
2371853030eSSimon Glass }
2381853030eSSimon Glass
2391853030eSSimon Glass if (trans->bytesout == 4) /* and bytesin is > 0 */
2401853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
2411853030eSSimon Glass
2421853030eSSimon Glass /* Fast read command is called with 5 bytes instead of 4 */
2431853030eSSimon Glass if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
2441853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
2451853030eSSimon Glass --trans->bytesout;
2461853030eSSimon Glass }
2471853030eSSimon Glass }
2481853030eSSimon Glass
spi_setup_opcode(struct ich_spi_priv * ctlr,struct spi_trans * trans,bool lock)2493e791416SBin Meng static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
2503e791416SBin Meng bool lock)
2511853030eSSimon Glass {
2521853030eSSimon Glass uint16_t optypes;
253ba457562SSimon Glass uint8_t opmenu[ctlr->menubytes];
2541853030eSSimon Glass
2551853030eSSimon Glass trans->opcode = trans->out[0];
2561853030eSSimon Glass spi_use_out(trans, 1);
2573e791416SBin Meng if (!lock) {
2581853030eSSimon Glass /* The lock is off, so just use index 0. */
259ba457562SSimon Glass ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
260ba457562SSimon Glass optypes = ich_readw(ctlr, ctlr->optype);
2611853030eSSimon Glass optypes = (optypes & 0xfffc) | (trans->type & 0x3);
262ba457562SSimon Glass ich_writew(ctlr, optypes, ctlr->optype);
2631853030eSSimon Glass return 0;
2641853030eSSimon Glass } else {
2651853030eSSimon Glass /* The lock is on. See if what we need is on the menu. */
2661853030eSSimon Glass uint8_t optype;
2671853030eSSimon Glass uint16_t opcode_index;
2681853030eSSimon Glass
2691853030eSSimon Glass /* Write Enable is handled as atomic prefix */
2701853030eSSimon Glass if (trans->opcode == SPI_OPCODE_WREN)
2711853030eSSimon Glass return 0;
2721853030eSSimon Glass
273ba457562SSimon Glass read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
274ba457562SSimon Glass for (opcode_index = 0; opcode_index < ctlr->menubytes;
2751853030eSSimon Glass opcode_index++) {
2761853030eSSimon Glass if (opmenu[opcode_index] == trans->opcode)
2771853030eSSimon Glass break;
2781853030eSSimon Glass }
2791853030eSSimon Glass
280ba457562SSimon Glass if (opcode_index == ctlr->menubytes) {
2811853030eSSimon Glass printf("ICH SPI: Opcode %x not found\n",
2821853030eSSimon Glass trans->opcode);
283ba457562SSimon Glass return -EINVAL;
2841853030eSSimon Glass }
2851853030eSSimon Glass
286ba457562SSimon Glass optypes = ich_readw(ctlr, ctlr->optype);
2871853030eSSimon Glass optype = (optypes >> (opcode_index * 2)) & 0x3;
2881853030eSSimon Glass if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
2891853030eSSimon Glass optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
2901853030eSSimon Glass trans->bytesout >= 3) {
2911853030eSSimon Glass /* We guessed wrong earlier. Fix it up. */
2921853030eSSimon Glass trans->type = optype;
2931853030eSSimon Glass }
2941853030eSSimon Glass if (optype != trans->type) {
2951853030eSSimon Glass printf("ICH SPI: Transaction doesn't fit type %d\n",
2961853030eSSimon Glass optype);
297ba457562SSimon Glass return -ENOSPC;
2981853030eSSimon Glass }
2991853030eSSimon Glass return opcode_index;
3001853030eSSimon Glass }
3011853030eSSimon Glass }
3021853030eSSimon Glass
spi_setup_offset(struct spi_trans * trans)3031853030eSSimon Glass static int spi_setup_offset(struct spi_trans *trans)
3041853030eSSimon Glass {
3059eb4339bSBin Meng /* Separate the SPI address and data */
3061853030eSSimon Glass switch (trans->type) {
3071853030eSSimon Glass case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
3081853030eSSimon Glass case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
3091853030eSSimon Glass return 0;
3101853030eSSimon Glass case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
3111853030eSSimon Glass case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
3121853030eSSimon Glass trans->offset = ((uint32_t)trans->out[0] << 16) |
3131853030eSSimon Glass ((uint32_t)trans->out[1] << 8) |
3141853030eSSimon Glass ((uint32_t)trans->out[2] << 0);
3151853030eSSimon Glass spi_use_out(trans, 3);
3161853030eSSimon Glass return 1;
3171853030eSSimon Glass default:
3181853030eSSimon Glass printf("Unrecognized SPI transaction type %#x\n", trans->type);
319ba457562SSimon Glass return -EPROTO;
3201853030eSSimon Glass }
3211853030eSSimon Glass }
3221853030eSSimon Glass
3231853030eSSimon Glass /*
3241853030eSSimon Glass * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
325472d5460SYork Sun * below is true) or 0. In case the wait was for the bit(s) to set - write
3261853030eSSimon Glass * those bits back, which would cause resetting them.
3271853030eSSimon Glass *
3281853030eSSimon Glass * Return the last read status value on success or -1 on failure.
3291853030eSSimon Glass */
ich_status_poll(struct ich_spi_priv * ctlr,u16 bitmask,int wait_til_set)330ba457562SSimon Glass static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
331ba457562SSimon Glass int wait_til_set)
3321853030eSSimon Glass {
3331853030eSSimon Glass int timeout = 600000; /* This will result in 6s */
3341853030eSSimon Glass u16 status = 0;
3351853030eSSimon Glass
3361853030eSSimon Glass while (timeout--) {
337ba457562SSimon Glass status = ich_readw(ctlr, ctlr->status);
3381853030eSSimon Glass if (wait_til_set ^ ((status & bitmask) == 0)) {
339ba457562SSimon Glass if (wait_til_set) {
340ba457562SSimon Glass ich_writew(ctlr, status & bitmask,
341ba457562SSimon Glass ctlr->status);
342ba457562SSimon Glass }
3431853030eSSimon Glass return status;
3441853030eSSimon Glass }
3451853030eSSimon Glass udelay(10);
3461853030eSSimon Glass }
3471853030eSSimon Glass
3481853030eSSimon Glass printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
3491853030eSSimon Glass status, bitmask);
350ba457562SSimon Glass return -ETIMEDOUT;
3511853030eSSimon Glass }
3521853030eSSimon Glass
ich_spi_config_opcode(struct udevice * dev)353b42711f9SBin Meng void ich_spi_config_opcode(struct udevice *dev)
354b42711f9SBin Meng {
355b42711f9SBin Meng struct ich_spi_priv *ctlr = dev_get_priv(dev);
356b42711f9SBin Meng
357b42711f9SBin Meng /*
358b42711f9SBin Meng * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
359b42711f9SBin Meng * to prevent accidental or intentional writes. Before they get
360b42711f9SBin Meng * locked down, these registers should be initialized properly.
361b42711f9SBin Meng */
362b42711f9SBin Meng ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
363b42711f9SBin Meng ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
364b42711f9SBin Meng ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
365b42711f9SBin Meng ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
366b42711f9SBin Meng }
367b42711f9SBin Meng
ich_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)368ba457562SSimon Glass static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
369ba457562SSimon Glass const void *dout, void *din, unsigned long flags)
3701853030eSSimon Glass {
371ba457562SSimon Glass struct udevice *bus = dev_get_parent(dev);
372e1e332c8SSimon Glass struct ich_spi_platdata *plat = dev_get_platdata(bus);
373ba457562SSimon Glass struct ich_spi_priv *ctlr = dev_get_priv(bus);
3741853030eSSimon Glass uint16_t control;
3751853030eSSimon Glass int16_t opcode_index;
3761853030eSSimon Glass int with_address;
3771853030eSSimon Glass int status;
3781853030eSSimon Glass int bytes = bitlen / 8;
379ba457562SSimon Glass struct spi_trans *trans = &ctlr->trans;
3801853030eSSimon Glass unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
3811853030eSSimon Glass int using_cmd = 0;
3823e791416SBin Meng bool lock = spi_lock_status(plat, ctlr->base);
383ba457562SSimon Glass int ret;
3841853030eSSimon Glass
3855d4a757cSSimon Glass /* We don't support writing partial bytes */
3861853030eSSimon Glass if (bitlen % 8) {
3871853030eSSimon Glass debug("ICH SPI: Accessing partial bytes not supported\n");
388ba457562SSimon Glass return -EPROTONOSUPPORT;
3891853030eSSimon Glass }
3901853030eSSimon Glass
3911853030eSSimon Glass /* An empty end transaction can be ignored */
3921853030eSSimon Glass if (type == SPI_XFER_END && !dout && !din)
3931853030eSSimon Glass return 0;
3941853030eSSimon Glass
3951853030eSSimon Glass if (type & SPI_XFER_BEGIN)
3961853030eSSimon Glass memset(trans, '\0', sizeof(*trans));
3971853030eSSimon Glass
3981853030eSSimon Glass /* Dp we need to come back later to finish it? */
3991853030eSSimon Glass if (dout && type == SPI_XFER_BEGIN) {
4001853030eSSimon Glass if (bytes > ICH_MAX_CMD_LEN) {
4011853030eSSimon Glass debug("ICH SPI: Command length limit exceeded\n");
402ba457562SSimon Glass return -ENOSPC;
4031853030eSSimon Glass }
4041853030eSSimon Glass memcpy(trans->cmd, dout, bytes);
4051853030eSSimon Glass trans->cmd_len = bytes;
406fffe25dbSSimon Glass debug_trace("ICH SPI: Saved %d bytes\n", bytes);
4071853030eSSimon Glass return 0;
4081853030eSSimon Glass }
4091853030eSSimon Glass
4101853030eSSimon Glass /*
4111853030eSSimon Glass * We process a 'middle' spi_xfer() call, which has no
4121853030eSSimon Glass * SPI_XFER_BEGIN/END, as an independent transaction as if it had
4131853030eSSimon Glass * an end. We therefore repeat the command. This is because ICH
4141853030eSSimon Glass * seems to have no support for this, or because interest (in digging
4151853030eSSimon Glass * out the details and creating a special case in the code) is low.
4161853030eSSimon Glass */
4171853030eSSimon Glass if (trans->cmd_len) {
4181853030eSSimon Glass trans->out = trans->cmd;
4191853030eSSimon Glass trans->bytesout = trans->cmd_len;
4201853030eSSimon Glass using_cmd = 1;
421fffe25dbSSimon Glass debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len);
4221853030eSSimon Glass } else {
4231853030eSSimon Glass trans->out = dout;
4241853030eSSimon Glass trans->bytesout = dout ? bytes : 0;
4251853030eSSimon Glass }
4261853030eSSimon Glass
4271853030eSSimon Glass trans->in = din;
4281853030eSSimon Glass trans->bytesin = din ? bytes : 0;
4291853030eSSimon Glass
4309eb4339bSBin Meng /* There has to always at least be an opcode */
4311853030eSSimon Glass if (!trans->bytesout) {
4321853030eSSimon Glass debug("ICH SPI: No opcode for transfer\n");
433ba457562SSimon Glass return -EPROTO;
4341853030eSSimon Glass }
4351853030eSSimon Glass
436ba457562SSimon Glass ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
437ba457562SSimon Glass if (ret < 0)
438ba457562SSimon Glass return ret;
4391853030eSSimon Glass
4406e670b5cSBin Meng if (plat->ich_version == ICHV_7)
441ba457562SSimon Glass ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
442e1e332c8SSimon Glass else
443e1e332c8SSimon Glass ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
4441853030eSSimon Glass
4451853030eSSimon Glass spi_setup_type(trans, using_cmd ? bytes : 0);
4463e791416SBin Meng opcode_index = spi_setup_opcode(ctlr, trans, lock);
4471853030eSSimon Glass if (opcode_index < 0)
448ba457562SSimon Glass return -EINVAL;
4491853030eSSimon Glass with_address = spi_setup_offset(trans);
4501853030eSSimon Glass if (with_address < 0)
451ba457562SSimon Glass return -EINVAL;
4521853030eSSimon Glass
4531853030eSSimon Glass if (trans->opcode == SPI_OPCODE_WREN) {
4541853030eSSimon Glass /*
4551853030eSSimon Glass * Treat Write Enable as Atomic Pre-Op if possible
4561853030eSSimon Glass * in order to prevent the Management Engine from
4571853030eSSimon Glass * issuing a transaction between WREN and DATA.
4581853030eSSimon Glass */
4593e791416SBin Meng if (!lock)
460ba457562SSimon Glass ich_writew(ctlr, trans->opcode, ctlr->preop);
4611853030eSSimon Glass return 0;
4621853030eSSimon Glass }
4631853030eSSimon Glass
464ba457562SSimon Glass if (ctlr->speed && ctlr->max_speed >= 33000000) {
4651853030eSSimon Glass int byte;
4661853030eSSimon Glass
467ba457562SSimon Glass byte = ich_readb(ctlr, ctlr->speed);
468ba457562SSimon Glass if (ctlr->cur_speed >= 33000000)
4691853030eSSimon Glass byte |= SSFC_SCF_33MHZ;
4701853030eSSimon Glass else
4711853030eSSimon Glass byte &= ~SSFC_SCF_33MHZ;
472ba457562SSimon Glass ich_writeb(ctlr, byte, ctlr->speed);
4731853030eSSimon Glass }
4741853030eSSimon Glass
4751853030eSSimon Glass /* See if we have used up the command data */
4761853030eSSimon Glass if (using_cmd && dout && bytes) {
4771853030eSSimon Glass trans->out = dout;
4781853030eSSimon Glass trans->bytesout = bytes;
479fffe25dbSSimon Glass debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes);
4801853030eSSimon Glass }
4811853030eSSimon Glass
4821853030eSSimon Glass /* Preset control fields */
4831853030eSSimon Glass control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
4841853030eSSimon Glass
4851853030eSSimon Glass /* Issue atomic preop cycle if needed */
486ba457562SSimon Glass if (ich_readw(ctlr, ctlr->preop))
4871853030eSSimon Glass control |= SPIC_ACS;
4881853030eSSimon Glass
4891853030eSSimon Glass if (!trans->bytesout && !trans->bytesin) {
4901853030eSSimon Glass /* SPI addresses are 24 bit only */
491ba457562SSimon Glass if (with_address) {
492ba457562SSimon Glass ich_writel(ctlr, trans->offset & 0x00FFFFFF,
493ba457562SSimon Glass ctlr->addr);
494ba457562SSimon Glass }
4951853030eSSimon Glass /*
4961853030eSSimon Glass * This is a 'no data' command (like Write Enable), its
4971853030eSSimon Glass * bitesout size was 1, decremented to zero while executing
4981853030eSSimon Glass * spi_setup_opcode() above. Tell the chip to send the
4991853030eSSimon Glass * command.
5001853030eSSimon Glass */
501ba457562SSimon Glass ich_writew(ctlr, control, ctlr->control);
5021853030eSSimon Glass
5031853030eSSimon Glass /* wait for the result */
504ba457562SSimon Glass status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
505ba457562SSimon Glass if (status < 0)
506ba457562SSimon Glass return status;
5071853030eSSimon Glass
5081853030eSSimon Glass if (status & SPIS_FCERR) {
5091853030eSSimon Glass debug("ICH SPI: Command transaction error\n");
510ba457562SSimon Glass return -EIO;
5111853030eSSimon Glass }
5121853030eSSimon Glass
5131853030eSSimon Glass return 0;
5141853030eSSimon Glass }
5151853030eSSimon Glass
5161853030eSSimon Glass /*
5171853030eSSimon Glass * Check if this is a write command atempting to transfer more bytes
5181853030eSSimon Glass * than the controller can handle. Iterations for writes are not
5191853030eSSimon Glass * supported here because each SPI write command needs to be preceded
5201853030eSSimon Glass * and followed by other SPI commands, and this sequence is controlled
5211853030eSSimon Glass * by the SPI chip driver.
5221853030eSSimon Glass */
523ba457562SSimon Glass if (trans->bytesout > ctlr->databytes) {
5241853030eSSimon Glass debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
525ba457562SSimon Glass return -EPROTO;
5261853030eSSimon Glass }
5271853030eSSimon Glass
5281853030eSSimon Glass /*
5291853030eSSimon Glass * Read or write up to databytes bytes at a time until everything has
5301853030eSSimon Glass * been sent.
5311853030eSSimon Glass */
5321853030eSSimon Glass while (trans->bytesout || trans->bytesin) {
5331853030eSSimon Glass uint32_t data_length;
5341853030eSSimon Glass
5351853030eSSimon Glass /* SPI addresses are 24 bit only */
536ba457562SSimon Glass ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
5371853030eSSimon Glass
5381853030eSSimon Glass if (trans->bytesout)
539ba457562SSimon Glass data_length = min(trans->bytesout, ctlr->databytes);
5401853030eSSimon Glass else
541ba457562SSimon Glass data_length = min(trans->bytesin, ctlr->databytes);
5421853030eSSimon Glass
5431853030eSSimon Glass /* Program data into FDATA0 to N */
5441853030eSSimon Glass if (trans->bytesout) {
545ba457562SSimon Glass write_reg(ctlr, trans->out, ctlr->data, data_length);
5461853030eSSimon Glass spi_use_out(trans, data_length);
5471853030eSSimon Glass if (with_address)
5481853030eSSimon Glass trans->offset += data_length;
5491853030eSSimon Glass }
5501853030eSSimon Glass
5511853030eSSimon Glass /* Add proper control fields' values */
552ba457562SSimon Glass control &= ~((ctlr->databytes - 1) << 8);
5531853030eSSimon Glass control |= SPIC_DS;
5541853030eSSimon Glass control |= (data_length - 1) << 8;
5551853030eSSimon Glass
5561853030eSSimon Glass /* write it */
557ba457562SSimon Glass ich_writew(ctlr, control, ctlr->control);
5581853030eSSimon Glass
5599eb4339bSBin Meng /* Wait for Cycle Done Status or Flash Cycle Error */
560ba457562SSimon Glass status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
561ba457562SSimon Glass if (status < 0)
562ba457562SSimon Glass return status;
5631853030eSSimon Glass
5641853030eSSimon Glass if (status & SPIS_FCERR) {
5655d4a757cSSimon Glass debug("ICH SPI: Data transaction error %x\n", status);
566ba457562SSimon Glass return -EIO;
5671853030eSSimon Glass }
5681853030eSSimon Glass
5691853030eSSimon Glass if (trans->bytesin) {
570ba457562SSimon Glass read_reg(ctlr, ctlr->data, trans->in, data_length);
5711853030eSSimon Glass spi_use_in(trans, data_length);
5721853030eSSimon Glass if (with_address)
5731853030eSSimon Glass trans->offset += data_length;
5741853030eSSimon Glass }
5751853030eSSimon Glass }
5761853030eSSimon Glass
5771853030eSSimon Glass /* Clear atomic preop now that xfer is done */
578d2ca80c3SBin Meng if (!lock)
579ba457562SSimon Glass ich_writew(ctlr, 0, ctlr->preop);
5801853030eSSimon Glass
5811853030eSSimon Glass return 0;
5821853030eSSimon Glass }
5831853030eSSimon Glass
ich_spi_probe(struct udevice * dev)584f2b85ab5SSimon Glass static int ich_spi_probe(struct udevice *dev)
585ba457562SSimon Glass {
586f2b85ab5SSimon Glass struct ich_spi_platdata *plat = dev_get_platdata(dev);
587f2b85ab5SSimon Glass struct ich_spi_priv *priv = dev_get_priv(dev);
588ba457562SSimon Glass uint8_t bios_cntl;
589ba457562SSimon Glass int ret;
590ba457562SSimon Glass
591f2b85ab5SSimon Glass ret = ich_init_controller(dev, plat, priv);
592ba457562SSimon Glass if (ret)
593ba457562SSimon Glass return ret;
594f2b85ab5SSimon Glass /* Disable the BIOS write protect so write commands are allowed */
595f2b85ab5SSimon Glass ret = pch_set_spi_protect(dev->parent, false);
596f2b85ab5SSimon Glass if (ret == -ENOSYS) {
59750787928SSimon Glass bios_cntl = ich_readb(priv, priv->bcr);
59869fd4c38SJagan Teki bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
599ba457562SSimon Glass bios_cntl |= 1; /* Write Protect Disable (WPD) */
60050787928SSimon Glass ich_writeb(priv, bios_cntl, priv->bcr);
601f2b85ab5SSimon Glass } else if (ret) {
602f2b85ab5SSimon Glass debug("%s: Failed to disable write-protect: err=%d\n",
603f2b85ab5SSimon Glass __func__, ret);
604f2b85ab5SSimon Glass return ret;
605ba457562SSimon Glass }
606ba457562SSimon Glass
607ab201074SBin Meng /* Lock down SPI controller settings if required */
608ab201074SBin Meng if (plat->lockdown) {
609ab201074SBin Meng ich_spi_config_opcode(dev);
610ab201074SBin Meng spi_lock_down(plat, priv->base);
611ab201074SBin Meng }
612ab201074SBin Meng
613ba457562SSimon Glass priv->cur_speed = priv->max_speed;
614ba457562SSimon Glass
615ba457562SSimon Glass return 0;
616ba457562SSimon Glass }
617ba457562SSimon Glass
ich_spi_remove(struct udevice * bus)6184759dffeSStefan Roese static int ich_spi_remove(struct udevice *bus)
6194759dffeSStefan Roese {
6204759dffeSStefan Roese /*
6214759dffeSStefan Roese * Configure SPI controller so that the Linux MTD driver can fully
6224759dffeSStefan Roese * access the SPI NOR chip
6234759dffeSStefan Roese */
624b42711f9SBin Meng ich_spi_config_opcode(bus);
6254759dffeSStefan Roese
6264759dffeSStefan Roese return 0;
6274759dffeSStefan Roese }
6284759dffeSStefan Roese
ich_spi_set_speed(struct udevice * bus,uint speed)629ba457562SSimon Glass static int ich_spi_set_speed(struct udevice *bus, uint speed)
630ba457562SSimon Glass {
631ba457562SSimon Glass struct ich_spi_priv *priv = dev_get_priv(bus);
632ba457562SSimon Glass
633ba457562SSimon Glass priv->cur_speed = speed;
634ba457562SSimon Glass
635ba457562SSimon Glass return 0;
636ba457562SSimon Glass }
637ba457562SSimon Glass
ich_spi_set_mode(struct udevice * bus,uint mode)638ba457562SSimon Glass static int ich_spi_set_mode(struct udevice *bus, uint mode)
639ba457562SSimon Glass {
640ba457562SSimon Glass debug("%s: mode=%d\n", __func__, mode);
641ba457562SSimon Glass
642ba457562SSimon Glass return 0;
643ba457562SSimon Glass }
644ba457562SSimon Glass
ich_spi_child_pre_probe(struct udevice * dev)645ba457562SSimon Glass static int ich_spi_child_pre_probe(struct udevice *dev)
646ba457562SSimon Glass {
647ba457562SSimon Glass struct udevice *bus = dev_get_parent(dev);
648ba457562SSimon Glass struct ich_spi_platdata *plat = dev_get_platdata(bus);
649ba457562SSimon Glass struct ich_spi_priv *priv = dev_get_priv(bus);
650bcbe3d15SSimon Glass struct spi_slave *slave = dev_get_parent_priv(dev);
651ba457562SSimon Glass
652ba457562SSimon Glass /*
653ba457562SSimon Glass * Yes this controller can only write a small number of bytes at
654ba457562SSimon Glass * once! The limit is typically 64 bytes.
655ba457562SSimon Glass */
656ba457562SSimon Glass slave->max_write_size = priv->databytes;
657ba457562SSimon Glass /*
658ba457562SSimon Glass * ICH 7 SPI controller only supports array read command
659ba457562SSimon Glass * and byte program command for SST flash
660ba457562SSimon Glass */
66108fe9c29SJagan Teki if (plat->ich_version == ICHV_7)
66208fe9c29SJagan Teki slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
663ba457562SSimon Glass
664ba457562SSimon Glass return 0;
665ba457562SSimon Glass }
666ba457562SSimon Glass
ich_spi_ofdata_to_platdata(struct udevice * dev)6671f9eb59dSBin Meng static int ich_spi_ofdata_to_platdata(struct udevice *dev)
6681f9eb59dSBin Meng {
6691f9eb59dSBin Meng struct ich_spi_platdata *plat = dev_get_platdata(dev);
670e160f7d4SSimon Glass int node = dev_of_offset(dev);
6711f9eb59dSBin Meng int ret;
6721f9eb59dSBin Meng
673e160f7d4SSimon Glass ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi");
6741f9eb59dSBin Meng if (ret == 0) {
6756e670b5cSBin Meng plat->ich_version = ICHV_7;
6761f9eb59dSBin Meng } else {
677e160f7d4SSimon Glass ret = fdt_node_check_compatible(gd->fdt_blob, node,
6781f9eb59dSBin Meng "intel,ich9-spi");
6791f9eb59dSBin Meng if (ret == 0)
6806e670b5cSBin Meng plat->ich_version = ICHV_9;
6811f9eb59dSBin Meng }
6821f9eb59dSBin Meng
683ab201074SBin Meng plat->lockdown = fdtdec_get_bool(gd->fdt_blob, node,
684ab201074SBin Meng "intel,spi-lock-down");
685ab201074SBin Meng
6861f9eb59dSBin Meng return ret;
6871f9eb59dSBin Meng }
6881f9eb59dSBin Meng
689ba457562SSimon Glass static const struct dm_spi_ops ich_spi_ops = {
690ba457562SSimon Glass .xfer = ich_spi_xfer,
691ba457562SSimon Glass .set_speed = ich_spi_set_speed,
692ba457562SSimon Glass .set_mode = ich_spi_set_mode,
693ba457562SSimon Glass /*
694ba457562SSimon Glass * cs_info is not needed, since we require all chip selects to be
695ba457562SSimon Glass * in the device tree explicitly
696ba457562SSimon Glass */
697ba457562SSimon Glass };
698ba457562SSimon Glass
699ba457562SSimon Glass static const struct udevice_id ich_spi_ids[] = {
7001f9eb59dSBin Meng { .compatible = "intel,ich7-spi" },
7011f9eb59dSBin Meng { .compatible = "intel,ich9-spi" },
702ba457562SSimon Glass { }
703ba457562SSimon Glass };
704ba457562SSimon Glass
705ba457562SSimon Glass U_BOOT_DRIVER(ich_spi) = {
706ba457562SSimon Glass .name = "ich_spi",
707ba457562SSimon Glass .id = UCLASS_SPI,
708ba457562SSimon Glass .of_match = ich_spi_ids,
709ba457562SSimon Glass .ops = &ich_spi_ops,
7101f9eb59dSBin Meng .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
711ba457562SSimon Glass .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
712ba457562SSimon Glass .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
713ba457562SSimon Glass .child_pre_probe = ich_spi_child_pre_probe,
714ba457562SSimon Glass .probe = ich_spi_probe,
7154759dffeSStefan Roese .remove = ich_spi_remove,
7164759dffeSStefan Roese .flags = DM_FLAG_OS_PREPARE,
717ba457562SSimon Glass };
718