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Searched refs:cs (Results 1 – 25 of 1620) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dgen8_engine_cs.c63 cs = gen8_emit_pipe_control(cs, 0, 0); in gen8_emit_flush_rcs()
237 cs = gen12_emit_pipe_control(cs, in mtl_dummy_pipe_control()
355 cs = gen12_emit_aux_table_inv(engine, cs); in gen12_emit_flush_rcs()
651 cs = emit_preempt_busywait(rq, cs); in gen8_emit_fini_breadcrumb_tail()
671 cs = gen8_emit_pipe_control(cs, in gen8_emit_fini_breadcrumb_rcs()
680 cs = gen8_emit_ggtt_write_rcs(cs, in gen8_emit_fini_breadcrumb_rcs()
691 cs = gen8_emit_pipe_control(cs, in gen11_emit_fini_breadcrumb_rcs()
701 cs = gen8_emit_ggtt_write_rcs(cs, in gen11_emit_fini_breadcrumb_rcs()
793 cs = ccs_emit_wa_busywait(rq, cs); in gen12_emit_fini_breadcrumb_tail()
824 cs = gen12_emit_pipe_control(cs, 0, in gen12_emit_fini_breadcrumb_rcs()
[all …]
H A Dgen6_engine_cs.c60 u32 *cs; in gen6_emit_post_sync_nonzero_flush() local
81 *cs++ = 0; in gen6_emit_post_sync_nonzero_flush()
82 *cs++ = 0; in gen6_emit_post_sync_nonzero_flush()
137 *cs++ = 0; in gen6_emit_flush_rcs()
148 *cs++ = 0; in gen6_emit_breadcrumb_rcs()
149 *cs++ = 0; in gen6_emit_breadcrumb_rcs()
234 u32 *cs; in gen6_emit_bb_start() local
244 cs = __gen6_emit_bb_start(cs, offset, security); in gen6_emit_bb_start()
256 u32 *cs; in hsw_emit_bb_start() local
266 cs = __gen6_emit_bb_start(cs, offset, security); in hsw_emit_bb_start()
[all …]
H A Dgen2_engine_cs.c19 u32 cmd, *cs; in gen2_emit_flush() local
29 *cs++ = cmd; in gen2_emit_flush()
33 *cs++ = 0; in gen2_emit_flush()
36 *cs++ = cmd; in gen2_emit_flush()
45 u32 cmd, *cs; in gen4_emit_flush_rcs() local
108 *cs++ = 0; in gen4_emit_flush_rcs()
109 *cs++ = 0; in gen4_emit_flush_rcs()
131 u32 *cs; in gen4_emit_flush_vcs() local
169 return cs; in __gen2_emit_breadcrumb()
255 u32 *cs; in gen3_emit_bb_start() local
[all …]
H A Dgen7_renderclear.c163 *cs++ = 0; in gen7_fill_surface_state()
164 *cs++ = 0; in gen7_fill_surface_state()
165 *cs++ = 0; in gen7_fill_surface_state()
184 *cs++ = 0; in gen7_fill_binding_table()
185 *cs++ = 0; in gen7_fill_binding_table()
186 *cs++ = 0; in gen7_fill_binding_table()
187 *cs++ = 0; in gen7_fill_binding_table()
188 *cs++ = 0; in gen7_fill_binding_table()
189 *cs++ = 0; in gen7_fill_binding_table()
298 *cs++ = count * 8 * sizeof(*cs); in gen7_emit_interface_descriptor_load()
[all …]
H A Dintel_migrate.c336 u32 *cs; in emit_no_arbitration() local
410 hdr = cs; in emit_pte()
443 hdr = cs; in emit_pte()
537 u32 *cs; in emit_copy_ccs() local
586 u32 *cs; in emit_copy() local
595 *cs++ = 0; in emit_copy()
599 *cs++ = 0; in emit_copy()
606 *cs++ = 0; in emit_copy()
610 *cs++ = 0; in emit_copy()
924 u32 *cs; in emit_clear() local
[all …]
/openbmc/qemu/hw/intc/
H A Darm_gicv3_redist.c242 update_for_all_lpis(cs, ptbase, ctbase, idbits, true, &cs->hppvlpi); in gicv3_redist_update_vlpi_only()
381 *data = gicr_read_bitmap_reg(cs, attrs, cs->gicr_ienabler0); in gicr_readl()
389 uint32_t val = cs->gicr_ipendr0 | (~cs->edge_trigger & cs->level); in gicr_readl()
395 *data = gicr_read_bitmap_reg(cs, attrs, cs->gicr_iactiver0); in gicr_readl()
417 value = cs->edge_trigger & mask_group(cs, attrs); in gicr_readl()
537 gicr_write_set_bitmap_reg(cs, attrs, &cs->gicr_ipendr0, value); in gicr_writel()
1018 update_for_one_lpi(cs, irq, ctbase, true, &cs->hppvlpi); in gicv3_redist_vlpi_pending()
1048 update_for_one_lpi(cs, irq, ctbase, true, &cs->hppvlpi); in gicv3_redist_process_vlpi()
1122 cs->level = deposit32(cs->level, irq, 1, level); in gicv3_redist_set_irq()
1137 int irqgrp = gicv3_irq_group(cs->gic, cs, irq); in gicv3_redist_send_sgi()
[all …]
H A Darm_gicv3_cpuif.c360 mask = icv_gprio_mask(cs, cs->hppvlpi.grp); in icv_hppvlpi_can_preempt()
891 return cs->hppi.prio == 0xff || (cs->icc_igrpen[cs->hppi.grp] == 0); in icc_no_enabled_hppi()
906 if (cs->hppi.prio >= cs->icc_pmr_el1) { in icc_hppi_can_preempt()
917 mask = icc_gprio_mask(cs, cs->hppi.grp); in icc_hppi_can_preempt()
1725 int grp = gicv3_irq_group(cs->gic, cs, irq); in icc_dir_write()
2223 cs->icc_bpr[GICV3_G0] = icc_min_bpr(cs); in icc_reset()
2224 cs->icc_bpr[GICV3_G1] = icc_min_bpr(cs); in icc_reset()
2225 cs->icc_bpr[GICV3_G1NS] = icc_min_bpr_ns(cs); in icc_reset()
2226 memset(cs->icc_apr, 0, sizeof(cs->icc_apr)); in icc_reset()
2232 memset(cs->ich_apr, 0, sizeof(cs->ich_apr)); in icc_reset()
[all …]
H A Darm_gicv3.c40 if (prio == cs->hppi.prio && irq <= cs->hppi.irq) { in irqbetter()
107 pend = cs->gicr_ipendr0 | (~cs->edge_trigger & cs->level); in gicr_int_pending()
165 cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq); in gicv3_redist_update_noirqset()
171 if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) { in gicv3_redist_update_noirqset()
172 cs->hppi.irq = cs->hpplpi.irq; in gicv3_redist_update_noirqset()
173 cs->hppi.prio = cs->hpplpi.prio; in gicv3_redist_update_noirqset()
174 cs->hppi.grp = cs->hpplpi.grp; in gicv3_redist_update_noirqset()
237 if (!cs) { in gicv3_update_noirqset()
266 cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq); in gicv3_update_noirqset()
269 if (!cs->seenbetter && cs->hppi.prio != 0xff && in gicv3_update_noirqset()
[all …]
/openbmc/qemu/target/i386/hvf/
H A Dx86hvf.c73 void hvf_put_xsave(CPUState *cs) in hvf_put_xsave() argument
98 vmx_update_tpr(cs); in hvf_put_segments()
265 hvf_put_xsave(cs); in hvf_put_registers()
267 hvf_put_segments(cs); in hvf_put_registers()
269 hvf_put_msrs(cs); in hvf_put_registers()
308 hvf_get_xsave(cs); in hvf_get_registers()
311 hvf_get_segments(cs); in hvf_get_registers()
312 hvf_get_msrs(cs); in hvf_get_registers()
430 if (!cs->vcpu_dirty) { in hvf_process_events()
447 cs->halted = 0; in hvf_process_events()
[all …]
/openbmc/linux/kernel/time/
H A Dclocksource.c186 cs->mark_unstable(cs); in __clocksource_unstable()
234 *csnow = cs->read(cs); in cs_watchdog_read()
334 csnow_mid = cs->read(cs); in clocksource_verify_one_cpu()
364 csnow_end = cs->read(cs); in clocksource_verify_percpu()
524 cs->tick_stable(cs); in clocksource_watchdog()
878 cs->suspend(cs); in clocksource_suspend()
890 cs->resume(cs); in clocksource_resume()
1176 while (freq && ((cs->mult + cs->maxadj < cs->mult) in __clocksource_update_freq_scale()
1177 || (cs->mult - cs->maxadj > cs->mult))) { in __clocksource_update_freq_scale()
1187 WARN_ONCE(cs->mult + cs->maxadj < cs->mult, in __clocksource_update_freq_scale()
[all …]
/openbmc/qemu/target/i386/tcg/sysemu/
H A Dsmm_helper.c38 CPUState *cs = CPU(cpu); in do_smm_enter() local
86 x86_stq_phys(cs, sm_state + 0x7ed0, env->efer); in do_smm_enter()
99 x86_stq_phys(cs, sm_state + 0x7f78, env->eip); in do_smm_enter()
101 x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]); in do_smm_enter()
102 x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]); in do_smm_enter()
104 x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]); in do_smm_enter()
105 x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]); in do_smm_enter()
114 x86_stl_phys(cs, sm_state + 0x7ff0, env->eip); in do_smm_enter()
197 CPUState *cs = env_cpu(env); in helper_rsm() local
297 x86_ldl_phys(cs, in helper_rsm()
[all …]
/openbmc/linux/kernel/cgroup/
H A Dcpuset.c316 cs->partition_root_state = -cs->partition_root_state; in make_partition_invalid()
514 cs = parent_cs(cs); in guarantee_online_cpus()
546 cs = parent_cs(cs); in guarantee_online_mems()
601 if (cs) { in alloc_cpumasks()
636 if (cs) { in free_cpumasks()
656 trial = kmemdup(cs, sizeof(*cs), GFP_KERNEL); in alloc_trial_cpuset()
677 kfree(cs); in free_cpuset()
3240 cs = kzalloc(sizeof(*cs), GFP_KERNEL); in cpuset_css_alloc()
3241 if (!cs) in cpuset_css_alloc()
4068 while (!(is_mem_exclusive(cs) || is_mem_hardwall(cs)) && parent_cs(cs)) in nearest_hardwall_ancestor()
[all …]
/openbmc/qemu/semihosting/
H A Dsyscalls.c136 complete(cs, -1, -len); in gdb_open()
312 complete(cs, 0, 0); in host_close()
333 complete(cs, ret, 0); in host_read()
373 complete(cs, ret, err); in host_lseek()
437 complete(cs, ret, err); in host_stat()
565 complete(cs, len, 0); in staticfile_read()
589 complete(cs, ret, 0); in staticfile_lseek()
619 complete(cs, ret, 0); in console_read()
675 complete(cs, cond, 0); in console_poll_one()
711 complete(cs, 0, 0); in semihost_sys_close()
[all …]
H A Darm-compat-semi.c217 TaskState *ts = cs->opaque; in get_swi_errno()
229 TaskState *ts = cs->opaque; in common_semi_cb()
235 common_semi_set_ret(cs, ret); in common_semi_cb()
275 common_semi_cb(cs, ret, err); in common_semi_istty_cb()
286 common_semi_cb(cs, ret, err); in common_semi_seek_cb()
307 if (cpu_memory_rw_debug(cs, common_semi_flen_buf(cs) + in common_semi_flen_fstat_cb()
318 common_semi_cb(cs, ret, err); in common_semi_flen_fstat_cb()
334 common_semi_cb(cs, ret, err); in common_semi_readc_cb()
373 args = common_semi_arg(cs, 1); in do_common_semihosting()
529 common_semi_set_ret(cs, 0); in do_common_semihosting()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_cmd.c29 *cs++ = 0; in pxp_emit_session_selection()
30 *cs++ = 0; in pxp_emit_session_selection()
41 *cs++ = 0; in pxp_emit_session_selection()
45 return cs; in pxp_emit_session_selection()
52 *cs++ = 0; in pxp_emit_inline_termination()
54 return cs; in pxp_emit_inline_termination()
59 cs = pxp_emit_session_selection(cs, idx); in pxp_emit_session_termination()
60 cs = pxp_emit_inline_termination(cs); in pxp_emit_session_termination()
101 u32 *cs; in intel_pxp_terminate_session() local
123 cs = pxp_emit_session_termination(cs, id); in intel_pxp_terminate_session()
[all …]
/openbmc/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c78 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
79 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
80 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
81 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
110 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
111 .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
112 .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
142 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
143 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
144 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
[all …]
/openbmc/linux/drivers/scsi/
H A Dmyrs.c116 cs->prev_cmd_mbox2 = cs->prev_cmd_mbox1; in myrs_qcmd()
515 cs->next_cmd_mbox = cs->first_cmd_mbox; in myrs_enable_mmio_mbox()
516 cs->prev_cmd_mbox1 = cs->last_cmd_mbox; in myrs_enable_mmio_mbox()
517 cs->prev_cmd_mbox2 = cs->last_cmd_mbox - 1; in myrs_enable_mmio_mbox()
531 cs->next_stat_mbox = cs->first_stat_mbox; in myrs_enable_mmio_mbox()
1537 cs->reset(cs->io_base); in myrs_host_reset()
2126 myrs_log_event(cs, cs->event_buf); in myrs_monitor()
2247 cs->fwstat_buf, cs->fwstat_addr); in myrs_unmap()
2271 cs->disable_intr(cs); in myrs_cleanup()
2276 free_irq(cs->irq, cs); in myrs_cleanup()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c106 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()
228 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
430 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
529 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
618 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
678 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
721 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
836 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
913 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
954 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
[all …]
H A Dddr3_read_leveling.c91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
97 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
121 cs, pup); in ddr3_read_leveling_hw()
128 (u32) cs, 1); in ddr3_read_leveling_hw()
202 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_sw()
619 * cs)); in ddr3_read_leveling_single_cs_rl_mode()
622 cs)); in ddr3_read_leveling_single_cs_rl_mode()
729 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_rl_mode()
1024 * cs)); in ddr3_read_leveling_single_cs_window_mode()
1027 cs)); in ddr3_read_leveling_single_cs_window_mode()
[all …]
/openbmc/qemu/linux-user/ppc/
H A Dcpu_loop.c70 CPUState *cs = env_cpu(env); in cpu_loop() local
77 cpu_exec_start(cs); in cpu_loop()
78 trapnr = cpu_exec(cs); in cpu_loop()
79 cpu_exec_end(cs); in cpu_loop()
80 process_queued_cpu_work(cs); in cpu_loop()
251 cpu_abort(cs, "Instruction segment exception " in cpu_loop()
256 cpu_abort(cs, "Hypervisor decrementer interrupt " in cpu_loop()
266 cpu_abort(cs, "Hypervisor data storage exception " in cpu_loop()
274 cpu_abort(cs, "Hypervisor data segment exception " in cpu_loop()
289 cpu_abort(cs, "Instruction fetch TLB exception " in cpu_loop()
[all …]
/openbmc/qemu/target/mips/
H A Dkvm.c44 return cs->cpu_index; in kvm_arch_vcpu_id()
64 int kvm_arch_init_vcpu(CPUState *cs) in kvm_arch_init_vcpu() argument
66 MIPSCPU *cpu = MIPS_CPU(cs); in kvm_arch_init_vcpu()
137 MIPSCPU *cpu = MIPS_CPU(cs); in kvm_arch_pre_run()
164 return cs->halted; in kvm_arch_process_async_events()
195 CPUState *cs = CPU(cpu); in kvm_mips_set_interrupt() local
215 CPUState *cs = current_cpu; in kvm_mips_set_ipi_interrupt() local
463 MIPSCPU *cpu = MIPS_CPU(cs); in kvm_mips_save_count()
557 CPUState *cs = opaque; in kvm_mips_update_state() local
566 if (!cs->vcpu_dirty) { in kvm_mips_update_state()
[all …]
/openbmc/linux/sound/core/
H A Dpcm_iec958.c34 memset(cs, 0, len); in snd_pcm_create_iec958_consumer_default()
37 cs[1] = IEC958_AES1_CON_GENERAL; in snd_pcm_create_iec958_consumer_default()
49 u8 *cs, size_t len) in fill_iec958_consumer() argument
83 cs[3] &= ~IEC958_AES3_CON_FS; in fill_iec958_consumer()
84 cs[3] |= fs; in fill_iec958_consumer()
112 cs[4] &= ~IEC958_AES4_CON_WORDLEN; in fill_iec958_consumer()
113 cs[4] |= ws; in fill_iec958_consumer()
134 u8 *cs, size_t len) in snd_pcm_fill_iec958_consumer() argument
138 cs, len); in snd_pcm_fill_iec958_consumer()
157 u8 *cs, size_t len) in snd_pcm_fill_iec958_consumer_hw_params() argument
[all …]
/openbmc/linux/include/linux/mfd/syscon/
H A Datmel-smc.h18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
32 #define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc) argument
33 #define ATMEL_HSMC_MODE(layout, cs) \ argument
64 #define ATMEL_HSMC_TIMINGS(layout, cs) \ argument
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/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c73 size = readl(&sdrc_base->cs[cs].mcfg) >> 8; in get_sdr_cs_size()
87 if (!cs) in get_sdr_cs_offset()
105 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
108 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); in write_sdrc_timings()
109 writel(CMD_NOP, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
110 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
111 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
112 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
113 writel(timings->mr, &sdrc_base->cs[cs].mr); in write_sdrc_timings()
119 if (!mem_ok(cs)) in write_sdrc_timings()
[all …]
/openbmc/qemu/target/i386/kvm/
H A Dxen-emu.c195 X86CPU *cpu = X86_CPU(cs); in kvm_xen_init_vcpu()
389 if (!cs) { in kvm_xen_get_vcpu_info_hva()
424 if (cs) { in kvm_xen_set_callback_asserted()
433 return cs && !!X86_CPU(cs)->env.xen_vcpu_callback_vector; in kvm_xen_has_vcpu_callback_vector()
441 if (!cs) { in kvm_xen_inject_vcpu_callback_vector()
467 qemu_cpu_kick(cs); in kvm_xen_inject_vcpu_callback_vector()
505 if (!cs) { in kvm_xen_set_vcpu_virq()
640 CPUState *cs = CPU(cpu); in do_add_to_physmap() local
672 CPUState *cs = CPU(cpu); in do_add_to_physmap_batch() local
757 CPUState *cs = CPU(cpu); in handle_set_param() local
[all …]

12345678910>>...65