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Searched refs:cs (Results 1 – 25 of 681) sorted by relevance

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/openbmc/qemu/hw/intc/
H A Darm_gicv3_redist.c17 static uint32_t mask_group(GICv3CPUState *cs, MemTxAttrs attrs) in mask_group() argument
24 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in mask_group()
26 return cs->gicr_igroupr0; in mask_group()
31 static int gicr_ns_access(GICv3CPUState *cs, int irq) in gicr_ns_access() argument
35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
38 static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, in gicr_write_bitmap_reg() argument
42 val &= mask_group(cs, attrs); in gicr_write_bitmap_reg()
44 gicv3_redist_update(cs); in gicr_write_bitmap_reg()
47 static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, in gicr_write_set_bitmap_reg() argument
51 val &= mask_group(cs, attrs); in gicr_write_set_bitmap_reg()
[all …]
H A Darm_gicv3.c24 static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio, bool nmi) in irqbetter() argument
33 if (prio != cs->hppi.prio) { in irqbetter()
34 return prio < cs->hppi.prio; in irqbetter()
41 if (nmi != cs->hppi.nmi) { in irqbetter()
49 if (irq <= cs->hppi.irq) { in irqbetter()
101 static uint32_t gicr_int_pending(GICv3CPUState *cs) in gicr_int_pending() argument
116 pend = cs->gicr_ipendr0 | (~cs->edge_trigger & cs->level); in gicr_int_pending()
117 pend &= cs->gicr_ienabler0; in gicr_int_pending()
118 pend &= ~cs->gicr_iactiver0; in gicr_int_pending()
120 if (cs->gic->gicd_ctlr & GICD_CTLR_DS) { in gicr_int_pending()
[all …]
/openbmc/qemu/target/i386/tcg/system/
H A Dsmm_helper.c38 CPUState *cs = CPU(cpu); in do_smm_enter() local
60 x86_stw_phys(cs, sm_state + offset, dt->selector); in do_smm_enter()
61 x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff); in do_smm_enter()
62 x86_stl_phys(cs, sm_state + offset + 4, dt->limit); in do_smm_enter()
63 x86_stq_phys(cs, sm_state + offset + 8, dt->base); in do_smm_enter()
66 x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base); in do_smm_enter()
67 x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit); in do_smm_enter()
69 x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector); in do_smm_enter()
70 x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base); in do_smm_enter()
71 x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit); in do_smm_enter()
[all …]
/openbmc/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c78 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
79 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
80 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
81 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
82 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
83 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
84 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
85 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
86 .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
110 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c46 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
106 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()
107 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
115 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw()
121 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw()
123 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw()
127 cs, pup); in ddr3_write_leveling_hw()
128 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw()
[all …]
H A Dddr3_read_leveling.c44 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
48 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
97 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
98 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
106 ddr3_read_pup_reg(PUP_RL_MODE, cs, in ddr3_read_leveling_hw()
111 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
116 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
121 cs, pup); in ddr3_read_leveling_hw()
[all …]
H A Dddr3_spd.c581 u32 cs, cl, cs_num, cs_ena; local
661 for (cs = 0; cs < MAX_CS; cs += 2) {
662 if (((1 << cs) & DIMM_CS_BITMAP) &&
663 !(cs_ena & (1 << cs))) {
665 cs_ena |= (0x1 << cs);
667 cs_ena |= (0x3 << cs);
669 cs_ena |= (0x7 << cs);
671 cs_ena |= (0xF << cs);
896 for (cs = 0; cs < MAX_CS; cs++) {
897 if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
[all …]
H A Dddr3_dfs.c117 u32 cs = 0; in ddr3_dfs_high_2_low() local
195 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
196 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
198 (cs << MR_CS_ADDR_OFFS)); in ddr3_dfs_high_2_low()
201 (cs << MR_CS_ADDR_OFFS), reg); in ddr3_dfs_high_2_low()
441 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
442 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_high_2_low()
443 reg &= ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_dfs_high_2_low()
467 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
468 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c40 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
68 u32 get_sdr_cs_size(u32 cs) in get_sdr_cs_size() argument
73 size = readl(&sdrc_base->cs[cs].mcfg) >> 8; in get_sdr_cs_size()
83 u32 get_sdr_cs_offset(u32 cs) in get_sdr_cs_offset() argument
87 if (!cs) in get_sdr_cs_offset()
101 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, in write_sdrc_timings() argument
105 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
108 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); in write_sdrc_timings()
109 writel(CMD_NOP, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
110 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
[all …]
/openbmc/qemu/qga/
H A Dguest-agent-command-state.c26 void ga_command_state_add(GACommandState *cs, in ga_command_state_add() argument
33 cs->groups = g_slist_append(cs->groups, cg); in ga_command_state_add()
46 void ga_command_state_init_all(GACommandState *cs) in ga_command_state_init_all() argument
48 g_assert(cs); in ga_command_state_init_all()
49 g_slist_foreach(cs->groups, ga_command_group_init, NULL); in ga_command_state_init_all()
62 void ga_command_state_cleanup_all(GACommandState *cs) in ga_command_state_cleanup_all() argument
64 g_assert(cs); in ga_command_state_cleanup_all()
65 g_slist_foreach(cs->groups, ga_command_group_cleanup, NULL); in ga_command_state_cleanup_all()
70 GACommandState *cs = g_new0(GACommandState, 1); in ga_command_state_new() local
71 cs->groups = NULL; in ga_command_state_new()
[all …]
/openbmc/qemu/target/s390x/
H A Dgdbstub.c31 int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) in s390_cpu_gdb_read_register() argument
33 CPUS390XState *env = cpu_env(cs); in s390_cpu_gdb_read_register()
46 int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) in s390_cpu_gdb_write_register() argument
48 CPUS390XState *env = cpu_env(cs); in s390_cpu_gdb_write_register()
71 static int cpu_read_ac_reg(CPUState *cs, GByteArray *buf, int n) in cpu_read_ac_reg() argument
73 S390CPU *cpu = S390_CPU(cs); in cpu_read_ac_reg()
84 static int cpu_write_ac_reg(CPUState *cs, uint8_t *mem_buf, int n) in cpu_write_ac_reg() argument
86 S390CPU *cpu = S390_CPU(cs); in cpu_write_ac_reg()
104 static int cpu_read_fp_reg(CPUState *cs, GByteArray *buf, int n) in cpu_read_fp_reg() argument
106 S390CPU *cpu = S390_CPU(cs); in cpu_read_fp_reg()
[all …]
/openbmc/qemu/hw/ssi/
H A Dbcm2835_spi.c37 if (s->cs & BCM2835_SPI_CS_INTD && s->cs & BCM2835_SPI_CS_DONE) { in bcm2835_spi_update_int()
41 if (s->cs & BCM2835_SPI_CS_INTR && s->cs & BCM2835_SPI_CS_RXR) { in bcm2835_spi_update_int()
51 s->cs |= BCM2835_SPI_CS_RXD; in bcm2835_spi_update_rx_flags()
53 s->cs &= ~BCM2835_SPI_CS_RXD; in bcm2835_spi_update_rx_flags()
58 s->cs |= BCM2835_SPI_CS_RXF; in bcm2835_spi_update_rx_flags()
60 s->cs &= ~BCM2835_SPI_CS_RXF; in bcm2835_spi_update_rx_flags()
65 s->cs |= BCM2835_SPI_CS_RXR; in bcm2835_spi_update_rx_flags()
67 s->cs &= ~BCM2835_SPI_CS_RXR; in bcm2835_spi_update_rx_flags()
75 s->cs &= ~BCM2835_SPI_CS_TXD; in bcm2835_spi_update_tx_flags()
77 s->cs |= BCM2835_SPI_CS_TXD; in bcm2835_spi_update_tx_flags()
[all …]
/openbmc/qemu/target/riscv/
H A Dgdbstub.c50 int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) in riscv_cpu_gdb_read_register() argument
52 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); in riscv_cpu_gdb_read_register()
53 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_cpu_gdb_read_register()
77 int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) in riscv_cpu_gdb_write_register() argument
79 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); in riscv_cpu_gdb_write_register()
80 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_cpu_gdb_write_register()
111 static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n) in riscv_gdb_get_fpu() argument
113 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_gdb_get_fpu()
127 static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n) in riscv_gdb_set_fpu() argument
129 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_gdb_set_fpu()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h118 #define CS_STRUCT_OFFS(cs) (CS_STRUCT_BASE + (cs) * 4) argument
121 #define CS_SIZE_OFFS(cs) (CS_SIZE_BASE + (cs) * 4) argument
124 #define CS_SIZE_HIGH_OFFS(cs) (CS_SIZE_HIGH_BASE + (cs)) argument
135 #define SDRAM_OP_CMD_CS_OFFS(cs) (SDRAM_OP_CMD_CS_BASE + (cs)) argument
231 #define RD_SMPL_DLY_CS_OFFS(cs) (RD_SMPL_DLY_CS_BASE + (cs) * 8) argument
236 #define RD_RDY_DLY_CS_OFFS(cs) (RD_RDY_DLY_CS_BASE + (cs) * 8) argument
268 #define CS_EXIST_OFFS(cs) (CS_EXIST_BASE + (cs)) argument
389 #define WL_PHY_REG(cs) (WL_PHY_BASE + (cs) * 0x4) argument
401 #define CTX_PHY_REG(cs) (CTX_PHY_BASE + (cs) * 0x4) argument
404 #define RL_PHY_REG(cs) (RL_PHY_BASE + (cs) * 0x4) argument
[all …]
/openbmc/u-boot/board/tqc/tqm834x/
H A Dtqm834x.c44 static long int get_ddr_bank_size(short cs, long *base);
45 static void set_cs_bounds(short cs, ulong base, ulong size);
46 static void set_cs_config(short cs, long config);
72 int cs; in dram_init() local
79 for(cs = 0; cs < 4; ++cs) { in dram_init()
80 set_cs_bounds(cs, in dram_init()
81 CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), in dram_init()
84 set_cs_config(cs, INITIAL_CS_CONFIG); in dram_init()
101 for(cs = 0; cs < 4; ++cs) { in dram_init()
102 debug("\nDetecting Bank%d\n", cs); in dram_init()
[all …]
/openbmc/qemu/target/i386/hvf/
H A Dx86hvf.h23 int hvf_process_events(CPUState *cs);
24 bool hvf_inject_interrupts(CPUState *cs);
25 void hvf_set_segment(CPUState *cs, struct vmx_segment *vmx_seg,
28 void hvf_put_xsave(CPUState *cs);
29 void hvf_put_msrs(CPUState *cs);
30 void hvf_get_xsave(CPUState *cs);
31 void hvf_get_msrs(CPUState *cs);
32 void vmx_clear_int_window_exiting(CPUState *cs);
33 void vmx_update_tpr(CPUState *cs);
/openbmc/u-boot/test/dm/
H A Dspi.c24 const int busnum = 0, cs = 0, mode = 0, speed = 1000000, cs_b = 1; in dm_test_spi_find() local
36 ut_assertok(spi_cs_info(bus, cs, &info)); in dm_test_spi_find()
45 ut_assertok(spi_cs_info(bus, cs, &info)); in dm_test_spi_find()
49 ut_asserteq(-ENODEV, spi_find_bus_and_cs(busnum, cs, &bus, &dev)); in dm_test_spi_find()
50 ut_asserteq(-ENODEV, spi_get_bus_and_cs(busnum, cs, speed, mode, in dm_test_spi_find()
59 ut_asserteq(-ENODEV, spi_find_bus_and_cs(busnum, cs, &bus, &dev)); in dm_test_spi_find()
60 ut_asserteq(-ENOENT, spi_get_bus_and_cs(busnum, cs, speed, mode, in dm_test_spi_find()
63 sandbox_sf_unbind_emul(state_get_current(), busnum, cs); in dm_test_spi_find()
64 ut_assertok(spi_cs_info(bus, cs, &info)); in dm_test_spi_find()
68 ut_assertok(sandbox_sf_bind_emul(state, busnum, cs, bus, node, in dm_test_spi_find()
[all …]
/openbmc/qemu/target/m68k/
H A Dm68k-semi.c78 static void m68k_semi_u32_cb(CPUState *cs, uint64_t ret, int err) in m68k_semi_u32_cb() argument
80 CPUM68KState *env = cpu_env(cs); in m68k_semi_u32_cb()
95 static void m68k_semi_u64_cb(CPUState *cs, uint64_t ret, int err) in m68k_semi_u64_cb() argument
97 CPUM68KState *env = cpu_env(cs); in m68k_semi_u64_cb()
128 CPUState *cs = env_cpu(env); in do_m68k_semihosting() local
143 semihost_sys_open(cs, m68k_semi_u32_cb, arg0, arg1, arg2, arg3); in do_m68k_semihosting()
148 semihost_sys_close(cs, m68k_semi_u32_cb, arg0); in do_m68k_semihosting()
155 semihost_sys_read(cs, m68k_semi_u32_cb, arg0, arg1, arg2); in do_m68k_semihosting()
162 semihost_sys_write(cs, m68k_semi_u32_cb, arg0, arg1, arg2); in do_m68k_semihosting()
170 semihost_sys_lseek(cs, m68k_semi_u64_cb, arg0, in do_m68k_semihosting()
[all …]
/openbmc/u-boot/drivers/memory/
H A Dti-aemif.c15 #define AEMIF_CONFIG(cs) (CONFIG_AEMIF_CNTRL_BASE + 0x10 \ argument
16 + (cs * 4))
37 static void aemif_configure(int cs, struct aemif_config *cfg) in aemif_configure() argument
43 tmp |= (1 << cs); in aemif_configure()
48 tmp |= (1 << cs); in aemif_configure()
52 tmp = __raw_readl(AEMIF_CONFIG(cs)); in aemif_configure()
65 __raw_writel(tmp, AEMIF_CONFIG(cs)); in aemif_configure()
70 int cs; in aemif_init() local
77 for (cs = 0; cs < num_cs; cs++) in aemif_init()
78 aemif_configure(cs, config + cs); in aemif_init()
/openbmc/u-boot/drivers/video/
H A Dhitachi_tx18d42vm_lcd.c18 static void lcd_panel_spi_write(int cs, int clk, int mosi, in lcd_panel_spi_write() argument
23 gpio_direction_output(cs, 0); in lcd_panel_spi_write()
32 gpio_direction_output(cs, 1); in lcd_panel_spi_write()
48 int i, cs, clk, mosi, ret = 0; in hitachi_tx18d42vm_init() local
50 cs = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS); in hitachi_tx18d42vm_init()
54 if (cs == -1 || clk == -1 || mosi == 1) { in hitachi_tx18d42vm_init()
59 if (gpio_request(cs, "tx18d42vm-spi-cs") != 0 || in hitachi_tx18d42vm_init()
68 lcd_panel_spi_write(cs, clk, mosi, init_data[i], 16); in hitachi_tx18d42vm_init()
72 lcd_panel_spi_write(cs, clk, mosi, 0x00ad, 16); /* display on */ in hitachi_tx18d42vm_init()
77 gpio_free(cs); in hitachi_tx18d42vm_init()
/openbmc/qemu/target/i386/tcg/
H A Dtcg-cpu.c32 static void x86_cpu_exec_enter(CPUState *cs) in x86_cpu_exec_enter() argument
34 X86CPU *cpu = X86_CPU(cs); in x86_cpu_exec_enter()
43 static void x86_cpu_exec_exit(CPUState *cs) in x86_cpu_exec_exit() argument
45 X86CPU *cpu = X86_CPU(cs); in x86_cpu_exec_exit()
51 static TCGTBCPUState x86_get_tb_cpu_state(CPUState *cs) in x86_get_tb_cpu_state() argument
53 CPUX86State *env = cpu_env(cs); in x86_get_tb_cpu_state()
70 static void x86_cpu_synchronize_from_tb(CPUState *cs, in x86_cpu_synchronize_from_tb() argument
75 CPUX86State *env = cpu_env(cs); in x86_cpu_synchronize_from_tb()
85 static void x86_restore_state_to_opc(CPUState *cs, in x86_restore_state_to_opc() argument
89 X86CPU *cpu = X86_CPU(cs); in x86_restore_state_to_opc()
[all …]
/openbmc/u-boot/board/freescale/ls1043ardb/
H A Dddr.h49 .cs[0].bnds = 0x0000007F,
50 .cs[1].bnds = 0,
51 .cs[2].bnds = 0,
52 .cs[3].bnds = 0,
53 .cs[0].config = 0x80040322,
54 .cs[0].config_2 = 0,
55 .cs[1].config = 0,
56 .cs[1].config_2 = 0,
57 .cs[2].config = 0,
58 .cs[3].config = 0,
/openbmc/qemu/target/alpha/
H A Dmem_helper.c41 void alpha_cpu_record_sigbus(CPUState *cs, vaddr addr, in alpha_cpu_record_sigbus() argument
44 do_unaligned_access(cpu_env(cs), addr, retaddr); in alpha_cpu_record_sigbus()
47 void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, in alpha_cpu_do_unaligned_access() argument
51 CPUAlphaState *env = cpu_env(cs); in alpha_cpu_do_unaligned_access()
54 cs->exception_index = EXCP_UNALIGN; in alpha_cpu_do_unaligned_access()
56 cpu_loop_exit(cs); in alpha_cpu_do_unaligned_access()
59 void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, in alpha_cpu_do_transaction_failed() argument
65 CPUAlphaState *env = cpu_env(cs); in alpha_cpu_do_transaction_failed()
69 cs->exception_index = EXCP_MCHK; in alpha_cpu_do_transaction_failed()
71 cpu_loop_exit_restore(cs, retaddr); in alpha_cpu_do_transaction_failed()
/openbmc/qemu/target/ppc/
H A Dgdbstub.c109 int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) in ppc_cpu_gdb_read_register() argument
111 CPUPPCState *env = cpu_env(cs); in ppc_cpu_gdb_read_register()
152 int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) in ppc_cpu_gdb_read_register_apple() argument
154 CPUPPCState *env = cpu_env(cs); in ppc_cpu_gdb_read_register_apple()
205 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) in ppc_cpu_gdb_write_register() argument
207 CPUPPCState *env = cpu_env(cs); in ppc_cpu_gdb_write_register()
251 int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n) in ppc_cpu_gdb_write_register_apple() argument
253 CPUPPCState *env = cpu_env(cs); in ppc_cpu_gdb_write_register_apple()
299 static void gdb_gen_spr_feature(CPUState *cs) in gdb_gen_spr_feature() argument
301 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); in gdb_gen_spr_feature()
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dmem-common.c42 u32 mem_ok(u32 cs) in mem_ok() argument
47 addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); in mem_ok()
63 void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, in enable_gpmc_cs_config() argument
66 writel(0, &cs->config7); in enable_gpmc_cs_config()
69 writel(gpmc_config[0], &cs->config1); in enable_gpmc_cs_config()
70 writel(gpmc_config[1], &cs->config2); in enable_gpmc_cs_config()
71 writel(gpmc_config[2], &cs->config3); in enable_gpmc_cs_config()
72 writel(gpmc_config[3], &cs->config4); in enable_gpmc_cs_config()
73 writel(gpmc_config[4], &cs->config5); in enable_gpmc_cs_config()
74 writel(gpmc_config[5], &cs->config6); in enable_gpmc_cs_config()
[all …]

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