/openbmc/qemu/target/ppc/ |
H A D | translate.c | 64 static TCGv cpu_gpr[32]; variable 1590 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], in gen_cmpb() 2007 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], in gen_mullw() 2046 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], in gen_mulli() 2076 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], in gen_mulld() 2227 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); in gen_neg() 2264 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], in gen_andi_() 2339 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); in gen_or() 2341 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); in gen_or() 2451 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], in gen_oris() [all …]
|
H A D | power8-pmu-regs.c.inc | 73 tcg_gen_andi_tl(t0, cpu_gpr[gprn], spr_mask); 98 tcg_gen_mov_tl(cpu_gpr[gprn], t0); 158 tcg_gen_mov_tl(cpu_gpr[gprn], t0); 183 gen_helper_read_pmc(cpu_gpr[gprn], tcg_env, t_sprn); 216 gen_helper_store_pmc(tcg_env, t_sprn, cpu_gpr[gprn]); 246 write_MMCR0_common(ctx, cpu_gpr[gprn]); 252 gen_helper_store_mmcr1(tcg_env, cpu_gpr[gprn]);
|
/openbmc/qemu/target/mips/tcg/ |
H A D | tx79_translate.c | 133 gen_logic_i64(cpu_gpr[a->rd], ax, bx); in trans_parallel_arith() 259 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen); in trans_parallel_compare() 465 tcg_gen_deposit_i64(cpu_gpr[a->rd], in trans_PEXTLx() 467 tcg_gen_deposit_i64(cpu_gpr[a->rd], in trans_PEXTLx() 564 tcg_gen_movi_i64(cpu_gpr[a->rd], 0); in trans_PCPYH() 569 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16, 16); in trans_PCPYH() 570 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32); in trans_PCPYH() 594 tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]); in trans_PCPYLD() 608 gen_load_gpr_hi(cpu_gpr[a->rd], a->rs); in trans_PCPYUD() 639 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32); in trans_PROT3W() [all …]
|
H A D | translate.c | 2600 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); in gen_arith() 2636 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); in gen_arith() 2670 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); in gen_arith() 2704 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); in gen_arith() 2716 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); in gen_arith() 2769 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); in gen_logic() 2776 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); in gen_logic() 2787 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); in gen_logic() 2798 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); in gen_logic() 3624 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); in gen_loongson_integer() [all …]
|
H A D | translate_addr_const.c | 30 tcg_gen_add_tl(cpu_gpr[rd], t0, t1); in gen_lsa() 31 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); in gen_lsa() 51 tcg_gen_add_tl(cpu_gpr[rd], t0, t1); in gen_dlsa()
|
H A D | octeon_translate.c | 59 tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff); in trans_BADDU() 77 tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1); in trans_DMUL() 148 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr[a->rd], t1, t0); in trans_SEQNE() 150 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0); in trans_SEQNE() 171 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm); in trans_SEQNEI() 173 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm); in trans_SEQNEI()
|
H A D | mips16e_translate.c.inc | 287 gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2); 301 gen_op_addr_add(ctx, t0, cpu_gpr[29], t2); 391 gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2); 590 tcg_gen_movi_tl(cpu_gpr[rx], (uint16_t) imm); 593 tcg_gen_xori_tl(cpu_gpr[24], cpu_gpr[rx], (uint16_t) imm); 1015 tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]); 1018 tcg_gen_ext16u_tl(cpu_gpr[rx], cpu_gpr[rx]); 1021 tcg_gen_ext8s_tl(cpu_gpr[rx], cpu_gpr[rx]); 1024 tcg_gen_ext16s_tl(cpu_gpr[rx], cpu_gpr[rx]); 1030 tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); [all …]
|
H A D | nanomips_translate.c.inc | 1061 gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], u); 1803 tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 8 * rd); 1806 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 1808 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 3413 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 3622 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm); 3626 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 3682 gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], offset); 3710 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt], addr_off); 3711 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); [all …]
|
H A D | translate.h | 185 extern TCGv cpu_gpr[32], cpu_PC;
|
H A D | micromips_translate.c.inc | 864 gen_load_gpr(cpu_gpr[rd], rs_rt_enc[enc_rs]); 865 gen_load_gpr(cpu_gpr[re], rs_rt_enc[enc_rt]); 1063 gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7); 3217 tcg_gen_movi_tl(cpu_gpr[reg], imm);
|
/openbmc/qemu/target/ppc/translate/ |
H A D | fixedpoint-impl.c.inc | 236 gen_op_cmp32(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf); 242 gen_op_cmp(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf); 244 gen_op_cmp32(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf); 367 gen_helper_CFUGED(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]); 407 do_cntzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb], false); 419 do_cntzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb], true); 431 gen_helper_PDEPD(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]); 443 gen_helper_PEXTD(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]); 487 gen_helper_CDTBCD(cpu_gpr[a->ra], cpu_gpr[a->rs]); 494 gen_helper_CBCDTD(cpu_gpr[a->ra], cpu_gpr[a->rs]); [all …]
|
H A D | spe-impl.c.inc | 28 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 65 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ 299 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 308 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 316 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 377 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 380 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 989 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1000 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1011 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], [all …]
|
H A D | storage-ctrl-impl.c.inc | 33 gen_helper_SLBIE(tcg_env, cpu_gpr[a->rb]); 47 gen_helper_SLBIEG(tcg_env, cpu_gpr[a->rb]); 89 gen_helper_SLBMTE(tcg_env, cpu_gpr[a->rb], cpu_gpr[a->rt]); 103 gen_helper_SLBMFEV(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]); 117 gen_helper_SLBMFEE(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]); 140 gen_helper_SLBFEE(cpu_gpr[a->rt], tcg_env, 141 cpu_gpr[a->rb]); 149 tcg_gen_movi_tl(cpu_gpr[a->rt], 0); 213 tcg_gen_ext32u_tl(t0, cpu_gpr[rb]); 222 gen_helper_tlbie_isa300(tcg_env, cpu_gpr[rb], cpu_gpr[a->rs], [all …]
|
H A D | processor-ctrl-impl.c.inc | 38 gen_helper_book3s_msgclr(tcg_env, cpu_gpr[a->rb]); 40 gen_helper_msgclr(tcg_env, cpu_gpr[a->rb]); 62 gen_helper_book3s_msgsnd(cpu_gpr[a->rb]); 64 gen_helper_msgsnd(cpu_gpr[a->rb]); 78 gen_helper_book3s_msgclrp(tcg_env, cpu_gpr[a->rb]); 91 gen_helper_book3s_msgsndp(tcg_env, cpu_gpr[a->rb]);
|
H A D | branch-impl.c.inc | 21 gen_helper_rfebb(tcg_env, cpu_gpr[arg->s]);
|
H A D | vsx-impl.c.inc | 478 tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0); 496 tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); 516 tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0); 538 tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); 542 tcg_gen_mov_i64(t0, cpu_gpr[rB(ctx->opcode)]); 562 tcg_gen_deposit_i64(t0, cpu_gpr[rA(ctx->opcode)], 1900 TCGv rt = cpu_gpr[rD(ctx->opcode)]; 1935 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1936 TCGv rb = cpu_gpr[rB(ctx->opcode)]; 1987 TCGv rt = cpu_gpr[rD(ctx->opcode)]; [all …]
|
H A D | vmx-impl.c.inc | 377 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \ 1794 tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], hi); 1812 tcg_gen_andi_tl(rc, cpu_gpr[a->rc], 0x1F); 1867 tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]); 1906 tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]); 2105 tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], lo); 2125 tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], tmp); 2144 tcg_gen_extu_tl_i64(t0, cpu_gpr[a->vrb]); 2203 tcg_gen_ext_tl_i64(tmp, cpu_gpr[a->vrb]); 2255 tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], r[0]); [all …]
|
H A D | fp-impl.c.inc | 1062 tcg_gen_mov_tl(cpu_gpr[ra], ea); 1087 return do_lsfpsd(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, single);
|
/openbmc/qemu/target/loongarch/ |
H A D | translate.c | 24 TCGv cpu_gpr[32], cpu_pc; variable 181 return cpu_gpr[reg_num]; in gpr_src() 184 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); in gpr_src() 188 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); in gpr_src() 199 return cpu_gpr[reg_num]; in gpr_dst() 207 tcg_gen_mov_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 210 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 213 tcg_gen_ext32u_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 358 cpu_gpr[0] = NULL; in loongarch_translate_init() 360 cpu_gpr[i] = tcg_global_mem_new(tcg_env, in loongarch_translate_init()
|
H A D | translate.h | 56 extern TCGv cpu_gpr[32], cpu_pc;
|
/openbmc/qemu/target/riscv/ |
H A D | translate.c | 352 return cpu_gpr[reg_num]; in get_gpr() 369 return cpu_gpr[reg_num]; in dest_gpr() 389 tcg_gen_mov_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 426 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); in gen_set_gpr128() 445 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); in get_fpr_hs() 451 return cpu_gpr[reg_num]; in get_fpr_hs() 471 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); in get_fpr_d() 476 return cpu_gpr[reg_num]; in get_fpr_d() 498 return cpu_gpr[reg_num]; in dest_fpr() 541 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); in gen_set_fpr_d() [all …]
|
/openbmc/qemu/target/riscv/insn_trans/ |
H A D | trans_rvzicbo.c.inc | 34 gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]); 41 gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]); 48 gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]); 55 gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
|
H A D | trans_rvv.c.inc | 3545 vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
|
/openbmc/qemu/target/loongarch/insn_trans/ |
H A D | trans_branch.c.inc | 15 tcg_gen_movi_tl(cpu_gpr[1], make_address_pc(ctx, ctx->base.pc_next + 4));
|