/openbmc/linux/drivers/pwm/ |
H A D | pwm-atmel-tcb.c | 43 u32 cmr; member 74 unsigned cmr; in atmel_tcb_pwm_request() local 87 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr); in atmel_tcb_pwm_request() 92 if (cmr & ATMEL_TC_WAVE) { in atmel_tcb_pwm_request() 102 tcbpwm->div = cmr & ATMEL_TC_TCCLKS; in atmel_tcb_pwm_request() 105 cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK | in atmel_tcb_pwm_request() 108 cmr = 0; in atmel_tcb_pwm_request() 110 cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0; in atmel_tcb_pwm_request() 111 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr); in atmel_tcb_pwm_request() 128 unsigned cmr; in atmel_tcb_pwm_disable() local [all …]
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H A D | pwm-atmel.c | 310 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_apply() local 314 pres = cmr & PWM_CMR_CPRE_MSK; in atmel_pwm_apply() 362 u32 sr, cmr; in atmel_pwm_get_state() local 365 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_get_state() 372 pres = cmr & PWM_CMR_CPRE_MSK; in atmel_pwm_get_state() 394 if (cmr & PWM_CMR_CPOL) in atmel_pwm_get_state()
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/openbmc/linux/drivers/counter/ |
H A D | microchip-tcb-capture.c | 87 u32 bmr, cmr; in mchp_tc_count_function_write() local 90 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr); in mchp_tc_count_function_write() 93 cmr &= ~ATMEL_TC_WAVE; in mchp_tc_count_function_write() 101 cmr |= ATMEL_TC_TIMER_CLOCK2; in mchp_tc_count_function_write() 103 cmr |= ATMEL_TC_TIMER_CLOCK1; in mchp_tc_count_function_write() 105 cmr |= ATMEL_TC_CMR_MASK; in mchp_tc_count_function_write() 106 cmr &= ~(ATMEL_TC_ABETRG | ATMEL_TC_XC0); in mchp_tc_count_function_write() 119 cmr |= ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_ABETRG | ATMEL_TC_XC0; in mchp_tc_count_function_write() 127 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr); in mchp_tc_count_function_write() 135 ATMEL_TC_REG(priv->channel[1], CMR), cmr); in mchp_tc_count_function_write() [all …]
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H A D | 104-quad-8.c | 62 u8 cmr[QUAD8_NUM_COUNTERS]; member 326 switch (u8_get_bits(priv->cmr[id], QUADRATURE_MODE)) { in quad8_function_get() 402 ret = quad8_control_register_update(priv->map, priv->cmr, id, mode_cfg, QUADRATURE_MODE); in quad8_function_write() 714 switch (u8_get_bits(priv->cmr[count->id], COUNT_MODE)) { in quad8_count_mode_read() 761 ret = quad8_control_register_update(priv->map, priv->cmr, count->id, count_mode, in quad8_count_mode_write() 854 switch (u8_get_bits(priv->cmr[count->id], COUNT_MODE)) { in quad8_count_ceiling_read() 882 switch (u8_get_bits(priv->cmr[count->id], COUNT_MODE)) { in quad8_count_ceiling_write() 1256 priv->cmr[channel] = SELECT_CMR | BINARY | u8_encode_bits(NORMAL_COUNT, COUNT_MODE) | in quad8_init_counter() 1258 ret = regmap_write(priv->map, QUAD8_CONTROL(channel), priv->cmr[channel]); in quad8_init_counter()
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/openbmc/qemu/hw/misc/ |
H A D | npcm7xx_pwm.c | 107 } else if (p->cmr >= p->cnr) { in npcm7xx_pwm_calculate_duty() 110 duty = (uint64_t)NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); in npcm7xx_pwm_calculate_duty() 302 value = s->pwm[npcm7xx_cmr_index(offset)].cmr; in npcm7xx_pwm_read() 382 p->cmr = NPCM7XX_MAX_CMR; in npcm7xx_pwm_write() 384 p->cmr = value; in npcm7xx_pwm_write() 459 p->cmr = 0x00000000; in npcm7xx_pwm_enter_reset() 519 VMSTATE_UINT32(cmr, NPCM7xxPWM),
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/openbmc/qemu/tests/qtest/ |
H A D | npcm7xx_pwm-test.c | 343 static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted) in pwm_compute_duty() argument 350 } else if (cmr >= cnr) { in pwm_compute_duty() 353 duty = (uint64_t)MAX_DUTY * (cmr + 1) / (cnr + 1); in pwm_compute_duty() 606 uint32_t ppr, csr, pcr, cnr, cmr; in test_toggle() local 627 cmr = cmr_list[l]; in test_toggle() 628 pwm_write_cmr(qts, td, cmr); in test_toggle() 630 expected_duty = pwm_compute_duty(cnr, cmr, false); in test_toggle() 637 g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr); in test_toggle() 650 expected_duty = pwm_compute_duty(cnr, cmr, true); in test_toggle()
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/openbmc/u-boot/include/ |
H A D | sja1000.h | 16 u8 cmr; member
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/openbmc/qemu/system/ |
H A D | memory.c | 1025 CoalescedMemoryRange *cmr, bool add) in flat_range_coalesced_io_notify() argument 1029 tmp = addrrange_shift(cmr->addr, in flat_range_coalesced_io_notify() 1050 CoalescedMemoryRange *cmr; in flat_range_coalesced_io_del() local 1052 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) { in flat_range_coalesced_io_del() 1053 flat_range_coalesced_io_notify(fr, as, cmr, false); in flat_range_coalesced_io_del() 1060 CoalescedMemoryRange *cmr; in flat_range_coalesced_io_add() local 1066 QTAILQ_FOREACH(cmr, &mr->coalesced, link) { in flat_range_coalesced_io_add() 1067 flat_range_coalesced_io_notify(fr, as, cmr, true); in flat_range_coalesced_io_add() 1077 CoalescedMemoryRange *cmr; in flat_range_coalesced_io_notify_listener_add_del() local 1081 QTAILQ_FOREACH(cmr, &mr->coalesced, link) { in flat_range_coalesced_io_notify_listener_add_del() [all …]
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/openbmc/qemu/include/hw/misc/ |
H A D | npcm7xx_pwm.h | 66 uint32_t cmr; member
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/openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
H A D | at91_tc.h | 11 u32 cmr; /* 0x04 Channel Mode Register */ member
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/openbmc/linux/drivers/clocksource/ |
H A D | timer-atmel-tcb.c | 44 u32 cmr; member 78 tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR)); in tc_clksrc_suspend() 94 writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR)); in tc_clksrc_resume()
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/openbmc/u-boot/arch/arm/mach-at91/arm920t/ |
H A D | timer.c | 41 writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr); in timer_init()
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/openbmc/u-boot/arch/m68k/include/asm/coldfire/ |
H A D | skha.h | 15 u32 cmr; /* 0x08 Command */ member
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/openbmc/u-boot/arch/arm/cpu/arm926ejs/armada100/ |
H A D | timer.c | 32 u32 cmr; member
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/openbmc/linux/drivers/scsi/lpfc/ |
H A D | lpfc.h | 223 uint32_t cmr : 1; /* Configure Max RPIs */ member 225 uint32_t cmr : 1; /* Configure Max RPIs */
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H A D | lpfc_hw.h | 3462 uint32_t cmr : 1; /* Configure Max RPIs */ member 3464 uint32_t cmr : 1; /* Configure Max RPIs */ member
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