/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/ |
H A D | dr_ste.c | 893 sizeof(raw_ip), clr); in dr_ste_copy_mask_spec() 902 sizeof(raw_ip), clr); in dr_ste_copy_mask_spec() 1008 IFC_GET_CLR(fte_match_set_misc5, mask, macsec_tag_0, clr); in dr_ste_copy_mask_misc5() 1028 bool clr) in mlx5dr_ste_copy_param() argument 1042 dr_ste_copy_mask_spec(buff, &set_param->outer, clr); in mlx5dr_ste_copy_param() 1055 dr_ste_copy_mask_misc(buff, &set_param->misc, clr); in mlx5dr_ste_copy_param() 1068 dr_ste_copy_mask_spec(buff, &set_param->inner, clr); in mlx5dr_ste_copy_param() 1081 dr_ste_copy_mask_misc2(buff, &set_param->misc2, clr); in mlx5dr_ste_copy_param() 1095 dr_ste_copy_mask_misc3(buff, &set_param->misc3, clr); in mlx5dr_ste_copy_param() 1109 dr_ste_copy_mask_misc4(buff, &set_param->misc4, clr); in mlx5dr_ste_copy_param() [all …]
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/openbmc/u-boot/arch/x86/include/asm/arch-quark/ |
H A D | msg_port.h | 111 & ~(clr)) | (set)) 113 #define msg_port_clrbits(port, reg, clr) \ argument 117 #define msg_port_clrsetbits(port, reg, clr, set) \ argument 120 #define msg_port_alt_clrbits(port, reg, clr) \ argument 121 msg_port_generic_clrsetbits(alt, port, reg, clr, 0) 124 #define msg_port_alt_clrsetbits(port, reg, clr, set) \ argument 125 msg_port_generic_clrsetbits(alt, port, reg, clr, set) 127 #define msg_port_io_clrbits(port, reg, clr) \ argument 128 msg_port_generic_clrsetbits(io, port, reg, clr, 0) 131 #define msg_port_io_clrsetbits(port, reg, clr, set) \ argument [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
H A D | hardware.h | 9 #define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | (set)) argument 11 #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) argument 15 #define rk_clrsetreg(addr, clr, set) \ argument 16 writel(((clr) | (set)) << 16 | (set), addr) 17 #define rk_clrreg(addr, clr) writel((clr) << 16, addr) argument
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/openbmc/linux/include/trace/events/ |
H A D | thp.h | 40 TP_PROTO(unsigned long addr, unsigned long pte, unsigned long clr, unsigned long set), 41 TP_ARGS(addr, pte, clr, set), 45 __field(unsigned long, clr) 52 __entry->clr = clr; 57 …and pte = 0x%lx clr = 0x%lx, set = 0x%lx", __entry->addr, __entry->pte, __entry->clr, __entry->set) 61 TP_PROTO(unsigned long addr, unsigned long pmd, unsigned long clr, unsigned long set), 62 TP_ARGS(addr, pmd, clr, set) 66 TP_PROTO(unsigned long addr, unsigned long pud, unsigned long clr, unsigned long set), 67 TP_ARGS(addr, pud, clr, set)
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/openbmc/u-boot/board/samsung/odroid/ |
H A D | odroid.c | 163 clrsetbits_le32(&clk->div_cpu0, clr, set); in board_clock_init() 175 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); in board_clock_init() 178 clrsetbits_le32(&clk->div_cpu1, clr, set); in board_clock_init() 248 clrsetbits_le32(&clk->div_dmc0, clr, set); in board_clock_init() 271 clrsetbits_le32(&clk->div_dmc1, clr, set); in board_clock_init() 291 clrsetbits_le32(&clk->src_peril0, clr, set); in board_clock_init() 304 clrsetbits_le32(&clk->div_peril0, clr, set); in board_clock_init() 323 clrsetbits_le32(&clk->div_fsys1, clr, set); in board_clock_init() 343 clrsetbits_le32(&clk->div_fsys2, clr, set); in board_clock_init() 350 clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); in board_clock_init() [all …]
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/openbmc/linux/arch/arm64/kvm/hyp/nvhe/ |
H A D | timer-sr.c | 42 u64 clr = 0, set = 0; in __timer_enable_traps() local 49 clr = CNTHCTL_EL1PCEN; in __timer_enable_traps() 54 clr |= CNTHCTL_EL1PCTEN; in __timer_enable_traps() 57 clr <<= 10; in __timer_enable_traps() 61 sysreg_clear_set(cnthctl_el2, clr, set); in __timer_enable_traps()
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/openbmc/linux/arch/sparc/lib/ |
H A D | ffs.S | 14 clr %o0 21 clr %o1 /* 2 */ 25 1: clr %o2 31 clr %o3 34 clr %o4 40 clr %o5
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/openbmc/linux/arch/arm/mach-rpc/ |
H A D | irq.c | 168 unsigned int irq, clr, set; in rpc_init_irq() local 181 clr = IRQ_NOREQUEST; in rpc_init_irq() 185 clr |= IRQ_NOPROBE; in rpc_init_irq() 195 irq_modify_status(irq, clr, set); in rpc_init_irq() 203 irq_modify_status(irq, clr, set); in rpc_init_irq() 211 irq_modify_status(irq, clr, set); in rpc_init_irq() 218 irq_modify_status(irq, clr, set); in rpc_init_irq()
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/openbmc/linux/drivers/clocksource/ |
H A D | timer-armada-370-xp.c | 88 static void local_timer_ctrl_clrset(u32 clr, u32 set) in local_timer_ctrl_clrset() argument 90 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, in local_timer_ctrl_clrset() 173 u32 clr = 0, set = 0; in armada_370_xp_timer_starting_cpu() local 178 clr = TIMER0_25MHZ; in armada_370_xp_timer_starting_cpu() 179 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_starting_cpu() 242 u32 clr = 0, set = 0; in armada_370_xp_timer_common_init() local 261 clr = TIMER0_25MHZ; in armada_370_xp_timer_common_init() 264 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); in armada_370_xp_timer_common_init() 265 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_common_init()
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/openbmc/linux/kernel/irq/ |
H A D | devres.c | 236 unsigned int clr; member 244 irq_remove_generic_chip(this->gc, this->msk, this->clr, this->set); in devm_irq_remove_generic_chip() 264 unsigned int clr, unsigned int set) in devm_irq_setup_generic_chip() argument 273 irq_setup_generic_chip(gc, msk, flags, clr, set); in devm_irq_setup_generic_chip() 277 dr->clr = clr; in devm_irq_setup_generic_chip()
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/openbmc/linux/arch/m68k/ifpsp060/src/ |
H A D | itest.S | 169 clr.l %d1 379 clr.l %d0 432 clr.l (%a0) 570 clr.l (%a0) 999 clr.l %d0 1013 # clr.l %d1 1260 clr.l %d0 1435 clr.l %d0 1961 clr.l %d0 2612 clr.l %d0 [all …]
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/openbmc/u-boot/drivers/net/ |
H A D | pic32_eth.c | 83 writel(EMAC_RMII_RESET, &emac_p->supp.clr); in pic32_mii_init() 141 writel(EMAC_FULLDUP, &emac_p->cfg2.clr); in pic32_mac_adjust_link() 150 writel(EMAC_RMII_SPD100, &emac_p->supp.clr); in pic32_mac_adjust_link() 196 writel(EMAC_RMII_SPD100, &emac_p->supp.clr); in pic32_mac_init() 248 writel(0xffffffff, &ectl_p->irq.clr); in pic32_ctrl_reset() 251 writel(0xffffffff, &ectl_p->txst.clr); in pic32_ctrl_reset() 252 writel(0xffffffff, &ectl_p->rxst.clr); in pic32_ctrl_reset() 255 writel(0x00ff, &ectl_p->rxfc.clr); in pic32_ctrl_reset() 362 writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_eth_stop() 373 writel(ETHCON_ON, &ectl_p->con1.clr); in pic32_eth_stop() [all …]
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/openbmc/linux/arch/powerpc/include/asm/ |
H A D | dcr-native.h | 112 unsigned clr, unsigned set) in __dcri_clrset() argument 120 val = (mfdcrx(base_data) & ~clr) | set; in __dcri_clrset() 124 val = (__mfdcr(base_data) & ~clr) | set; in __dcri_clrset() 138 #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ argument 140 reg, clr, set)
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H A D | code-patching.h | 93 static inline int modify_instruction(unsigned int *addr, unsigned int clr, in modify_instruction() argument 96 return patch_instruction(addr, ppc_inst((*addr & ~clr) | set)); in modify_instruction() 99 static inline int modify_instruction_site(s32 *site, unsigned int clr, unsigned int set) in modify_instruction_site() argument 101 return modify_instruction((unsigned int *)patch_site_addr(site), clr, set); in modify_instruction_site()
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/openbmc/u-boot/drivers/video/ |
H A D | console_rotate.c | 14 static int console_set_row_1(struct udevice *dev, uint row, int clr) in console_set_row_1() argument 30 *dst++ = clr; in console_set_row_1() 39 *dst++ = clr; in console_set_row_1() 48 *dst++ = clr; in console_set_row_1() 146 static int console_set_row_2(struct udevice *dev, uint row, int clr) in console_set_row_2() argument 161 *dst++ = clr; in console_set_row_2() 170 *dst++ = clr; in console_set_row_2() 179 *dst++ = clr; in console_set_row_2() 288 *dst++ = clr; in console_set_row_3() 297 *dst++ = clr; in console_set_row_3() [all …]
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H A D | console_normal.c | 16 static int console_normal_set_row(struct udevice *dev, uint row, int clr) in console_normal_set_row() argument 30 *dst++ = clr; in console_normal_set_row() 39 *dst++ = clr; in console_normal_set_row() 48 *dst++ = clr; in console_normal_set_row()
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/openbmc/linux/arch/m68k/ifpsp060/ |
H A D | os.S | 94 clr.l %d1 | return success 101 clr.l %d1 | return success 127 clr.l %d1 | return success 134 clr.l %d1 | return success 151 clr.l %d0 | clear whole longword 152 clr.l %d1 | assume success 187 clr.l %d1 | assume success 223 clr.l %d1 | assume success 245 clr.l %d1 | assume success 267 clr.l %d1 | assume success [all …]
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/openbmc/linux/drivers/net/wireless/ath/ath9k/ |
H A D | ar9003_wow.c | 127 u32 set, clr; in ath9k_hw_wow_apply_pattern() local 160 clr = AR_WOW_LENGTH1_MASK(pattern_count); in ath9k_hw_wow_apply_pattern() 161 REG_RMW(ah, AR_WOW_LENGTH1, set, clr); in ath9k_hw_wow_apply_pattern() 165 clr = AR_WOW_LENGTH2_MASK(pattern_count); in ath9k_hw_wow_apply_pattern() 166 REG_RMW(ah, AR_WOW_LENGTH2, set, clr); in ath9k_hw_wow_apply_pattern() 170 clr = AR_WOW_LENGTH3_MASK(pattern_count); in ath9k_hw_wow_apply_pattern() 171 REG_RMW(ah, AR_WOW_LENGTH3, set, clr); in ath9k_hw_wow_apply_pattern() 175 clr = AR_WOW_LENGTH4_MASK(pattern_count); in ath9k_hw_wow_apply_pattern() 176 REG_RMW(ah, AR_WOW_LENGTH4, set, clr); in ath9k_hw_wow_apply_pattern()
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/openbmc/linux/arch/m68k/math-emu/ |
H A D | fp_util.S | 70 2: clr.l %d0 99 clr.l %d1 | sign defaults to zero 109 clr.l (%a0) 116 clr.l (%a0)+ 117 clr.l (%a0)+ 118 clr.l (%a0) 142 clr.l (%a0) | low lword = 0
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/openbmc/linux/arch/powerpc/include/asm/book3s/64/ |
H A D | radix.h | 154 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr, in __radix_pte_update() argument 166 : "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr)) in __radix_pte_update() 174 pte_t *ptep, unsigned long clr, in radix__pte_update() argument 180 old_pte = __radix_pte_update(ptep, clr, set); in radix__pte_update() 286 pmd_t *pmdp, unsigned long clr, 289 pud_t *pudp, unsigned long clr,
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/openbmc/u-boot/common/ |
H A D | lcd_console_rotation.c | 31 static inline void console_setrow90(struct console_t *pcons, u32 row, int clr) in console_setrow90() argument 40 *dst-- = clr; in console_setrow90() 86 static inline void console_setrow180(struct console_t *pcons, u32 row, int clr) in console_setrow180() argument 94 *dst++ = clr; in console_setrow180() 133 static inline void console_setrow270(struct console_t *pcons, u32 row, int clr) in console_setrow270() argument 141 *dst++ = clr; in console_setrow270()
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/openbmc/u-boot/drivers/spi/ |
H A D | bcm63xx_hsspi.c | 142 uint32_t clr, set; in bcm63xx_hsspi_activate_cs() local 153 clr = SPI_PFL_SIG_LAUNCHRIS_MASK | in bcm63xx_hsspi_activate_cs() 167 clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); in bcm63xx_hsspi_activate_cs() 171 clr = 0; in bcm63xx_hsspi_activate_cs() 175 clr |= BIT(plat->cs); in bcm63xx_hsspi_activate_cs() 181 clr |= BIT(!plat->cs); in bcm63xx_hsspi_activate_cs() 185 clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set); in bcm63xx_hsspi_activate_cs()
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/openbmc/u-boot/drivers/gpio/ |
H A D | pic32_gpio.c | 57 writel(mask, &priv->regs->port.clr); in pic32_gpio_set_value() 81 writel(mask, &priv->regs->ansel.clr); in pic32_gpio_direction_input() 93 writel(mask, &priv->regs->ansel.clr); in pic32_gpio_direction_output() 94 writel(mask, &priv->regs->tris.clr); in pic32_gpio_direction_output()
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/openbmc/linux/drivers/gpu/drm/nouveau/dispnv50/ |
H A D | wndw.c | 130 union nv50_wndw_atom_mask clr = { in nv50_wndw_flush_clr() local 133 if (clr.sema ) wndw->func-> sema_clr(wndw); in nv50_wndw_flush_clr() 134 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); in nv50_wndw_flush_clr() 135 if (clr.xlut ) wndw->func-> xlut_clr(wndw); in nv50_wndw_flush_clr() 136 if (clr.csc ) wndw->func-> csc_clr(wndw); in nv50_wndw_flush_clr() 137 if (clr.image) wndw->func->image_clr(wndw); in nv50_wndw_flush_clr() 413 asyw->clr.xlut = armw->xlut.handle != 0; in nv50_wndw_atomic_check_lut() 428 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check_lut() 507 if (asyw->clr.xlut && asyw->visible) in nv50_wndw_atomic_check() 509 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check() [all …]
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/openbmc/linux/arch/mips/pic32/pic32mzda/ |
H A D | config.c | 71 u32 clr, set; in pic32_set_sdhci_adma_fifo_threshold() local 73 clr = (0x3ff << 4) | (0x3ff << 16); in pic32_set_sdhci_adma_fifo_threshold() 75 return pic32_conf_modify_atomic(PIC32_CFGCON2, clr, set); in pic32_set_sdhci_adma_fifo_threshold()
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