Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16 |
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#
1e5daf55 |
| 09-Mar-2023 |
Erez Shitrit <erezsh@nvidia.com> |
net/mlx5: DR, Fix crc32 calculation to work on big-endian (BE) CPUs
When calculating crc for hash index we use the function crc32 that calculates for little-endian (LE) arch. Then we convert it to n
net/mlx5: DR, Fix crc32 calculation to work on big-endian (BE) CPUs
When calculating crc for hash index we use the function crc32 that calculates for little-endian (LE) arch. Then we convert it to network endianness using htonl(), but it's wrong to do the conversion in BE archs since the crc32 value is already LE.
The solution is to switch the bytes from the crc result for all types of arc.
Fixes: 40416d8ede65 ("net/mlx5: DR, Replace CRC32 implementation to use kernel lib") Signed-off-by: Erez Shitrit <erezsh@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64 |
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#
2533e726 |
| 29-Aug-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Split chunk allocation to HW-dependent ways
This way we are able to allocate chunk for modify_headers from 2 types: STEv0 that is allocated from the action area, and STEv1 that is allo
net/mlx5: DR, Split chunk allocation to HW-dependent ways
This way we are able to allocate chunk for modify_headers from 2 types: STEv0 that is allocated from the action area, and STEv1 that is allocating the chunks from the special area for patterns.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
1207a772 |
| 29-Nov-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add function that tells if STE miss addr has been initialized
Up until now miss address in all the STEs was used to connect miss lists and to link the last STE in the list to end ancho
net/mlx5: DR, Add function that tells if STE miss addr has been initialized
Up until now miss address in all the STEs was used to connect miss lists and to link the last STE in the list to end anchor. Match range STE will require special handling because its miss address is part of the 'action'. That is, range action has hit and miss addresses. Since the range action is always the last action, need to make sure that its miss address isn't overwritten by the end anchor.
Adding new function mlx5dr_ste_is_miss_addr_set() to answer the question whether the STE's miss address has already been set as part of STE initialization. Use a callback that always returns false right now. Once match range is added, a different callback will be used for that STE type.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Erez Shitrit <erezsh@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44 |
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#
fb628b71 |
| 25-May-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Allocate htbl from its own slab allocator
SW steering allocates/frees lots of htbl structs. Create a separate kmem_cache and allocate htbls from this allocator.
Signed-off-by: Yevgeny
net/mlx5: DR, Allocate htbl from its own slab allocator
SW steering allocates/frees lots of htbl structs. Create a separate kmem_cache and allocate htbls from this allocator.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18 |
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#
0d7f1595 |
| 27-Jan-2022 |
Rongwei Liu <rongweil@nvidia.com> |
net/mlx5: DR, Remove hw_ste from mlx5dr_ste to reduce memory
It can be calculated via function mlx5dr_ste_get_hw_ste(). Very simple and lightweight, no need to use a dedicated member.
Reduce 8 byte
net/mlx5: DR, Remove hw_ste from mlx5dr_ste to reduce memory
It can be calculated via function mlx5dr_ste_get_hw_ste(). Very simple and lightweight, no need to use a dedicated member.
Reduce 8 bytes from struct mlx5dr_ste and its size is 48 bytes now.
Signed-off-by: Rongwei Liu <rongweil@nvidia.com> Reviewed-by: Shun Hao <shunh@nvidia.com> Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
597534bd |
| 27-Jan-2022 |
Rongwei Liu <rongweil@nvidia.com> |
net/mlx5: DR, Remove 4 members from mlx5dr_ste_htbl to reduce memory
Remove chunk_size in struct mlx5dr_icm_chunk and use chunk->size instead.
Remove ste_arr/hw_ste_arr/miss_list since they can be
net/mlx5: DR, Remove 4 members from mlx5dr_ste_htbl to reduce memory
Remove chunk_size in struct mlx5dr_icm_chunk and use chunk->size instead.
Remove ste_arr/hw_ste_arr/miss_list since they can be accessed from htbl->chunk pointer, no need to keep a copy.
This commit reduces 28 bytes from struct mlx5dr_ste_htbl and its size is 32 bytes now.
Signed-off-by: Rongwei Liu <rongweil@nvidia.com> Reviewed-by: Shun Hao <shunh@nvidia.com> Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
f51bb517 |
| 27-Jan-2022 |
Rongwei Liu <rongweil@nvidia.com> |
net/mlx5: DR, Remove num_of_entries byte_size from struct mlx5_dr_icm_chunk
Target to reduce the memory consumption in large scale of flow rules.
They can be calculated quickly from buddy memory po
net/mlx5: DR, Remove num_of_entries byte_size from struct mlx5_dr_icm_chunk
Target to reduce the memory consumption in large scale of flow rules.
They can be calculated quickly from buddy memory pool. 1. num_of_entries calls dr_icm_pool_get_chunk_num_of_entries(). 2. byte_size calls dr_icm_pool_get_chunk_byte_size().
Use chunk size in dr_icm_chunk to speed up and the one in dr_ste_htbl will be removed in the upcoming commit.
This commit reduce 8 bytes from struct mlx5_dr_icm_chunk and its current size is 56 bytes.
Signed-off-by: Rongwei Liu <rongweil@nvidia.com> Reviewed-by: Shun Hao <shunh@nvidia.com> Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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5c4f9b6e |
| 27-Jan-2022 |
Rongwei Liu <rongweil@nvidia.com> |
net/mlx5: DR, Remove icm_addr from mlx5dr_icm_chunk to reduce memory
It can be calculated quickly from buddy memory pool by function mlx5dr_icm_pool_get_chunk_icm_addr(). This function is very light
net/mlx5: DR, Remove icm_addr from mlx5dr_icm_chunk to reduce memory
It can be calculated quickly from buddy memory pool by function mlx5dr_icm_pool_get_chunk_icm_addr(). This function is very lightweight and straightforward.
Reduce 8 bytes and current size of struct mlx5_dr_icm_chunk is 64 bytes.
Signed-off-by: Rongwei Liu <rongweil@nvidia.com> Reviewed-by: Shun Hao <shunh@nvidia.com> Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
003f4f9a |
| 27-Jan-2022 |
Rongwei Liu <rongweil@nvidia.com> |
net/mlx5: DR, Remove mr_addr rkey from struct mlx5dr_icm_chunk
Reduce memory footprint by removing mr_addr and rkey from mlx5_dr_icm_chunk. 1. mr_addr is calculated by mlx5dr_icm_pool_get_chunk_mr_a
net/mlx5: DR, Remove mr_addr rkey from struct mlx5dr_icm_chunk
Reduce memory footprint by removing mr_addr and rkey from mlx5_dr_icm_chunk. 1. mr_addr is calculated by mlx5dr_icm_pool_get_chunk_mr_addr() 2. rkey is calculated by mlx5dr_icm_pool_get_chunk_rkey() The two new functions are very lightweight and straightforward.
Reduce 8 bytes from struct mlx5_dr_icm_chunk, its current size is 72 bytes.
Signed-off-by: Rongwei Liu <rongweil@nvidia.com> Reviewed-by: Shun Hao <shunh@nvidia.com> Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
6862c787 |
| 23-Feb-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for ConnectX-7 steering
Add support for a new SW format version that is implemented by ConnectX-7.
Except for several differences, the STEv2 is identical to STEv1, so for
net/mlx5: DR, Add support for ConnectX-7 steering
Add support for a new SW format version that is implemented by ConnectX-7.
Except for several differences, the STEv2 is identical to STEv1, so for most callbacks the STEv2 context struct will call STEv1 functions.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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638a07f1 |
| 23-Feb-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Refactor ste_ctx handling for STE v0/1
As preparation for supporting ConnectX-7, this patches changes handling of ste_ctx handling for existing STE v0 and V1: - each context is now a
net/mlx5: DR, Refactor ste_ctx handling for STE v0/1
As preparation for supporting ConnectX-7, this patches changes handling of ste_ctx handling for existing STE v0 and V1: - each context is now a static struct, and it has a corresponding getter - v0 and v1 were extended to contain the fields that are required for integrating STEv2.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
5c422bfa |
| 23-Feb-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for matching on Internet Header Length (IHL)
Add support for matching on new field - Internet Header Length (IHL).
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Si
net/mlx5: DR, Add support for matching on Internet Header Length (IHL)
Add support for matching on new field - Internet Header Length (IHL).
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v5.15.17, v5.4.173, v5.15.16, v5.15.15 |
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#
ffb0753b |
| 13-Jan-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Don't allow match on IP w/o matching on full ethertype/ip_version
Currently SMFS allows adding rule with matching on src/dst IP w/o matching on full ethertype or ip_version, which is n
net/mlx5: DR, Don't allow match on IP w/o matching on full ethertype/ip_version
Currently SMFS allows adding rule with matching on src/dst IP w/o matching on full ethertype or ip_version, which is not supported by HW. This patch fixes this issue and adds the check as it is done in DMFS.
Fixes: 26d688e33f88 ("net/mlx5: DR, Add Steering entry (STE) utilities") Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2 |
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#
f59464e2 |
| 07-Nov-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for matching on geneve_tlv_option_0_exist field
Match on geneve_tlv_option_0_exist field on devices that support STEv1.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.co
net/mlx5: DR, Add support for matching on geneve_tlv_option_0_exist field
Match on geneve_tlv_option_0_exist field on devices that support STEv1.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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Revision tags: v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63 |
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#
09753bab |
| 05-Sep-2021 |
Muhammad Sammar <muhammads@nvidia.com> |
net/mlx5: DR, Support matching on tunnel headers 0 and 1
Tunnel headers are generic encapsulation headers, applies for all tunneling protocols identified by the device native parser or by the progra
net/mlx5: DR, Support matching on tunnel headers 0 and 1
Tunnel headers are generic encapsulation headers, applies for all tunneling protocols identified by the device native parser or by the programmable parser, this support will enable raw matching headers 0 and 1.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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8c2b4fee |
| 05-Sep-2021 |
Muhammad Sammar <muhammads@nvidia.com> |
net/mlx5: DR, Add misc5 to match_param structs
Add misc5 match params to enable matching tunnel headers.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
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Revision tags: v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49 |
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#
941f1979 |
| 05-Jul-2021 |
Muhammad Sammar <muhammads@nvidia.com> |
net/mlx5: DR, Add check for unsupported fields in match param
When a matcher is being built, we "consume" (clear) mask fields one by one, and to verify that we do support all the required fields we
net/mlx5: DR, Add check for unsupported fields in match param
When a matcher is being built, we "consume" (clear) mask fields one by one, and to verify that we do support all the required fields we check if the whole mask was consumed, else the matching request includes unsupported fields.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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#
837b0d2e |
| 13-Jan-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Don't allow match on IP w/o matching on full ethertype/ip_version
commit ffb0753b954763d94f52c901adfe58ed0d4005e6 upstream.
Currently SMFS allows adding rule with matching on src/dst
net/mlx5: DR, Don't allow match on IP w/o matching on full ethertype/ip_version
commit ffb0753b954763d94f52c901adfe58ed0d4005e6 upstream.
Currently SMFS allows adding rule with matching on src/dst IP w/o matching on full ethertype or ip_version, which is not supported by HW. This patch fixes this issue and adds the check as it is done in DMFS.
Fixes: 26d688e33f88 ("net/mlx5: DR, Add Steering entry (STE) utilities") Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
8a015bae |
| 08-Jul-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Improve rule tracking memory consumption
To track each STE of the rule a rule member was allocated, each member would point to one STE. This means that we would allocate 40B (rule memb
net/mlx5: DR, Improve rule tracking memory consumption
To track each STE of the rule a rule member was allocated, each member would point to one STE. This means that we would allocate 40B (rule member) * number of STEs per rule.
To reduce this per rule allocation we use the STE tree pointers for next_htbl and pointing STE to navigate the tree, this allows us to keep only the pointer to the last STE of rule (always unique). From the last rule STE we are able to traverse and rebuild all of the STEs that construct the rule.
In our testing with 8M rules, each consisting of 7 STES, we were able to reduce 1.6GB of memory.
Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Erez Shitrit <erezsh@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
32c8e3b2 |
| 04-Jul-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Remove rehash ctrl struct from dr_htbl
The calculations to decide for the maximum allowed collision threshold are simple and there is no reason to save them on the htbl struct.
Signed
net/mlx5: DR, Remove rehash ctrl struct from dr_htbl
The calculations to decide for the maximum allowed collision threshold are simple and there is no reason to save them on the htbl struct.
Signed-off-by: Erez Shitrit <erezsh@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
46f2a8ae |
| 04-Jul-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Remove HW specific STE type from nic domain
Instead of using the HW specific STEv0 type, it is better to use an enum to indicate if this is an RX or TX nic domain. This means that now
net/mlx5: DR, Remove HW specific STE type from nic domain
Instead of using the HW specific STEv0 type, it is better to use an enum to indicate if this is an RX or TX nic domain. This means that now we will need to convert the nic domain type to the corresponding STE type.
Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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#
df9dd15a |
| 06-Feb-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for matching tunnel GTP-U
Enable matching on tunnel GTP-U and GTP-U first extension header using dynamic flex parser.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
net/mlx5: DR, Add support for matching tunnel GTP-U
Enable matching on tunnel GTP-U and GTP-U first extension header using dynamic flex parser.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
35ba005d |
| 06-Feb-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Set flex parser for TNL_MPLS dynamically
Query the flex_parser id that's intended for TNL_MPLS and use an appropriate flex parser for MPLS over UDP/GRE.
Signed-off-by: Muhammad Sammar
net/mlx5: DR, Set flex parser for TNL_MPLS dynamically
Query the flex_parser id that's intended for TNL_MPLS and use an appropriate flex parser for MPLS over UDP/GRE.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
3442e033 |
| 06-Feb-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for matching on geneve TLV option
Enable matching on tunnel geneve TLV option using the flex parser.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Y
net/mlx5: DR, Add support for matching on geneve TLV option
Enable matching on tunnel geneve TLV option using the flex parser.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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4923938d |
| 06-Feb-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Set STEv0 ICMP flex parser dynamically
Set the flex parser ID dynamicly for ICMP instead of relying on hardcoded values.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-o
net/mlx5: DR, Set STEv0 ICMP flex parser dynamically
Set the flex parser ID dynamicly for ICMP instead of relying on hardcoded values.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
show more ...
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