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Searched refs:clk_pll (Results 1 – 25 of 51) sorted by relevance

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/openbmc/linux/drivers/clk/mxs/
H A Dclk-pll.c23 struct clk_pll { struct
30 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
34 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare()
45 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare()
52 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable()
61 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable()
69 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
85 struct clk_pll *pll; in mxs_clk_pll()
/openbmc/linux/arch/m68k/coldfire/
H A Dm523x.c32 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
34 CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
35 CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
36 CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
37 CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
H A Dm528x.c34 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
36 CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
37 CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
38 CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
39 CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
H A Dm527x.c33 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
35 CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
36 CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
37 CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
38 CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
H A Dm5407.c29 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
H A Dm5206.c29 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
H A Dm5307.c38 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
H A Dm54xx.c38 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
H A Dm525x.c29 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
H A Dm5272.c40 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
H A Dm5249.c29 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
/openbmc/linux/drivers/clk/qcom/
H A Dclk-pll.c26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable()
67 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable()
82 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
128 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_determine_rate()
143 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate()
179 static int wait_for_pll(struct clk_pll *pll) in wait_for_pll()
203 struct clk_pll *p = to_clk_pll(clk_hw_get_parent(hw)); in clk_pll_vote_enable()
218 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap, in clk_pll_configure()
245 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, in clk_pll_configure_sr()
265 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_sr2_enable()
[all …]
H A Dclk-pll.h39 struct clk_pll { struct
59 #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr) argument
76 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
78 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
/openbmc/linux/drivers/clk/at91/
H A Dclk-pll.c32 #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
34 struct clk_pll { struct
57 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() argument
100 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_is_prepared()
107 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare()
116 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
237 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_round_rate()
246 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate()
266 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_save_context()
278 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_restore_context()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmoxa,moxart-clock.txt37 clk_pll: clk_pll@98100000 {
47 clocks = <&clk_pll>;
/openbmc/linux/drivers/clk/
H A Dclk-nomadik.c145 struct clk_pll { struct
164 #define to_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
169 struct clk_pll *pll = to_pll(hw); in pll_clk_enable()
189 struct clk_pll *pll = to_pll(hw); in pll_clk_disable()
208 struct clk_pll *pll = to_pll(hw); in pll_clk_is_enabled()
224 struct clk_pll *pll = to_pll(hw); in pll_clk_recalc_rate()
264 struct clk_pll *pll; in pll_clk_register()
H A Dclk-versaclock3.c691 static struct vc3_hw_data clk_pll[] = { variable
750 { .hw = &clk_pll[VC3_PLL1].hw },
754 { .hw = &clk_pll[VC3_PLL2].hw },
755 { .hw = &clk_pll[VC3_PLL3].hw }
758 { .hw = &clk_pll[VC3_PLL2].hw },
836 &clk_pll[VC3_PLL1].hw
890 &clk_pll[VC3_PLL3].hw
1047 for (i = 0; i < ARRAY_SIZE(clk_pll); i++) { in vc3_probe()
1048 clk_pll[i].regmap = regmap; in vc3_probe()
1049 ret = devm_clk_hw_register(dev, &clk_pll[i].hw); in vc3_probe()
[all …]
H A Dclk-vt8500.c41 struct clk_pll { struct
308 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
549 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_set_rate()
600 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_round_rate()
639 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_recalc_rate()
677 struct clk_pll *pll_clk; in vtwm_pll_clk_init()
/openbmc/linux/drivers/clk/spear/
H A Dclk-vco-pll.c63 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
84 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_round_rate_index()
124 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
144 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate()
280 struct clk_pll *pll; in clk_register_vco_pll()
/openbmc/linux/arch/arm/boot/dts/moxa/
H A Dmoxart.dtsi47 clk_pll: clk_pll@98100000 { label
57 clocks = <&clk_pll>;
/openbmc/linux/drivers/clk/keystone/
H A Dpll.c68 struct clk_pll { struct
73 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
78 struct clk_pll *pll = to_clk_pll(hw); in clk_pllclk_recalc()
126 struct clk_pll *pll; in clk_register_pll()
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dclock.c71 static struct clk_pll *get_pll(enum clock_id clkid) in get_pll()
92 struct clk_pll *pll = get_pll(clkid); in clock_ll_read_pll()
116 struct clk_pll *pll = NULL; in clock_start_pll()
265 struct clk_pll *pll = get_pll(clkid); in clock_set_pllout()
534 struct clk_pll *pll; in clock_get_rate()
591 struct clk_pll *pll; in clock_set_rate()
674 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH); in clock_verify()
/openbmc/linux/drivers/gpu/drm/imx/ipuv3/
H A Dimx-ldb.c103 struct clk *clk_pll[2]; /* upstream clock we can adjust */ member
172 clk_get_rate(ldb->clk_pll[chno]), serial_clk); in imx_ldb_set_clock()
173 clk_set_rate(ldb->clk_pll[chno], serial_clk); in imx_ldb_set_clock()
176 clk_get_rate(ldb->clk_pll[chno])); in imx_ldb_set_clock()
428 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname); in imx_ldb_get_clk()
430 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]); in imx_ldb_get_clk()
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-pllfh.h58 struct mtk_clk_pll clk_pll; member
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclk_rst.h11 struct clk_pll { struct
77 struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */

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