1 // SPDX-License-Identifier: GPL-2.0
2 /***************************************************************************/
3
4 /*
5 * 525x.c -- platform support for ColdFire 525x based boards
6 *
7 * Copyright (C) 2012, Steven King <sfking@fdwdc.com>
8 */
9
10 /***************************************************************************/
11
12 #include <linux/clkdev.h>
13 #include <linux/kernel.h>
14 #include <linux/param.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/platform_device.h>
18 #include <asm/machdep.h>
19 #include <asm/coldfire.h>
20 #include <asm/mcfsim.h>
21 #include <asm/mcfclk.h>
22
23 /***************************************************************************/
24
25 DEFINE_CLK(pll, "pll.0", MCF_CLK);
26 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
27
28 static struct clk_lookup m525x_clk_lookup[] = {
29 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
30 CLKDEV_INIT(NULL, "sys.0", &clk_sys),
31 CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
32 CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
33 CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
34 CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
35 CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
36 CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
37 CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),
38 };
39
40 /***************************************************************************/
41
m525x_qspi_init(void)42 static void __init m525x_qspi_init(void)
43 {
44 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
45 /* set the GPIO function for the qspi cs gpios */
46 /* FIXME: replace with pinmux/pinctl support */
47 u32 f = readl(MCFSIM2_GPIOFUNC);
48 f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
49 writel(f, MCFSIM2_GPIOFUNC);
50
51 /* QSPI irq setup */
52 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
53 MCFSIM_QSPIICR);
54 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
55 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
56 }
57
m525x_i2c_init(void)58 static void __init m525x_i2c_init(void)
59 {
60 #if IS_ENABLED(CONFIG_I2C_IMX)
61 u32 r;
62
63 /* first I2C controller uses regular irq setup */
64 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
65 MCFSIM_I2CICR);
66 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
67
68 /* second I2C controller is completely different */
69 r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
70 r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
71 r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
72 writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
73 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
74 }
75
76 /***************************************************************************/
77
config_BSP(char * commandp,int size)78 void __init config_BSP(char *commandp, int size)
79 {
80 mach_sched_init = hw_timer_init;
81
82 m525x_qspi_init();
83 m525x_i2c_init();
84
85 clkdev_add_table(m525x_clk_lookup, ARRAY_SIZE(m525x_clk_lookup));
86 }
87
88 /***************************************************************************/
89