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Searched refs:cgs_read_register (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_acp.c453 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); in acp_hw_init()
460 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); in acp_hw_init()
472 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); in acp_hw_init()
479 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); in acp_hw_init()
490 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); in acp_hw_init()
522 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); in acp_hw_fini()
529 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); in acp_hw_fini()
540 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); in acp_hw_fini()
547 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); in acp_hw_fini()
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Diceland_smumgr.c1308 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) in iceland_populate_single_memory_level()
1309 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in iceland_populate_single_memory_level()
1311 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; in iceland_populate_single_memory_level()
1317 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in iceland_populate_single_memory_level()
1600 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); in iceland_populate_memory_timing_parameters()
1601 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); in iceland_populate_memory_timing_parameters()
2371 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); in iceland_get_memory_modile_index()
2523 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS); in iceland_set_mc_special_registers()
2535 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); in iceland_set_mc_special_registers()
2564 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1); in iceland_set_mc_special_registers()
[all …]
H A Dci_smumgr.c151 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0); in ci_copy_bytes_to_smc()
204 *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0); in ci_read_smc_sram_dword()
1262 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) in ci_populate_single_memory_level()
1263 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()
1271 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()
1639 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); in ci_populate_memory_timing_parameters()
1640 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); in ci_populate_memory_timing_parameters()
2444 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); in ci_get_memory_modile_index()
2596 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS); in ci_set_mc_special_registers()
2608 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); in ci_set_mc_special_registers()
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H A Dtonga_smumgr.c2401 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) & in tonga_init_smc_table()
2988 temp_reg = cgs_read_register(hwmgr->device, in tonga_set_mc_special_registers()
3086 cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY)); in tonga_initialize_mc_reg_table()
3102 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS)); in tonga_initialize_mc_reg_table()
3104 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS)); in tonga_initialize_mc_reg_table()
3106 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1)); in tonga_initialize_mc_reg_table()
3108 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0)); in tonga_initialize_mc_reg_table()
3110 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1)); in tonga_initialize_mc_reg_table()
3112 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0)); in tonga_initialize_mc_reg_table()
3118 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2)); in tonga_initialize_mc_reg_table()
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H A Dsmu8_smumgr.c61 return cgs_read_register(hwmgr->device, in smu8_get_argument()
80 uint32_t val = cgs_read_register(hwmgr->device, in smu8_send_msg_to_smc_with_parameter()
161 (cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA) & firmware)) in smu8_check_fw_load_finish()
191 tmp = cgs_read_register(hwmgr->device, in smu8_load_mec_firmware()
197 tmp = cgs_read_register(hwmgr->device, in smu8_load_mec_firmware()
746 hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA); in smu8_start_smu()
H A Dsmu7_smumgr.c125 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11); in smu7_copy_bytes_to_smc()
208 return cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); in smu7_get_argument()
271 *value = result ? 0 : cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11); in smu7_read_smc_sram_dword()
H A Dfiji_smumgr.c1508 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); in fiji_populate_memory_timing_parameters()
1509 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); in fiji_populate_memory_timing_parameters()
1510 burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME); in fiji_populate_memory_timing_parameters()
2072 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) & in fiji_init_smc_table()
2524 cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING)); in fiji_initialize_mc_reg_table()
2526 cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING)); in fiji_initialize_mc_reg_table()
2528 cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2)); in fiji_initialize_mc_reg_table()
2530 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1)); in fiji_initialize_mc_reg_table()
2532 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0)); in fiji_initialize_mc_reg_table()
2534 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1)); in fiji_initialize_mc_reg_table()
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H A Dvegam_smumgr.c1262 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); in vegam_populate_memory_timing_parameters()
1263 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); in vegam_populate_memory_timing_parameters()
1264 burst_time = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME); in vegam_populate_memory_timing_parameters()
1265 rfsh_rate = cgs_read_register(hwmgr->device, mmMC_ARB_RFSH_RATE); in vegam_populate_memory_timing_parameters()
1266 misc3 = cgs_read_register(hwmgr->device, mmMC_ARB_MISC3); in vegam_populate_memory_timing_parameters()
2086 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) & in vegam_init_smc_table()
H A Dpolaris10_smumgr.c1478 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); in polaris10_populate_memory_timing_parameters()
1479 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); in polaris10_populate_memory_timing_parameters()
2078 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) in polaris10_init_smc_table()
2565 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); in polaris10_get_memory_modile_index()
/openbmc/linux/drivers/gpu/drm/amd/acp/
H A Dacp_hw.c43 acp_mode = cgs_read_register(cgs_device, in amd_acp_hw_init()
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dcgs_common.h131 …cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg,…
165 #define cgs_read_register(dev,offset) \ macro
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.h152 PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
164 cgs_read_register(device, mm##reg), reg, field, fieldval))
H A Dsmu7_hwmgr.c551 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); in smu7_copy_and_switch_arb_sets()
1286 (cgs_read_register(hwmgr->device, 0x1488) & ~0x1)); in smu7_start_dpm()
4804 cgs_read_register(hwmgr->device, mmDLL_CNTL); in smu7_read_clock_registers()
4806 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL); in smu7_read_clock_registers()
4808 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL); in smu7_read_clock_registers()
4810 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL); in smu7_read_clock_registers()
4812 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL); in smu7_read_clock_registers()
4814 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1); in smu7_read_clock_registers()
4816 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2); in smu7_read_clock_registers()
4818 cgs_read_register(hwmgr->device, mmMPLL_SS1); in smu7_read_clock_registers()
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H A Dsmu_helper.c122 cur_value = cgs_read_register(hwmgr->device, index); in phm_wait_on_register()
166 cur_value = cgs_read_register(hwmgr->device, in phm_wait_for_register_unequal()
H A Dsmu7_powertune.c924 data = cgs_read_register(hwmgr->device, config_regs->offset); in smu7_program_pt_config_registers()
976 value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX); in smu7_enable_didt_config()
H A Dvega10_powertune.c790 data = cgs_read_register(hwmgr->device, config_regs->offset); in vega10_program_gc_didt_config_registers()
/openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c10921 value = cgs_read_register(ctx->cgs_device, address); in dm_read_reg_func()