1e098bc96SEvan Quan /*
2e098bc96SEvan Quan * Copyright 2016 Advanced Micro Devices, Inc.
3e098bc96SEvan Quan *
4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a
5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"),
6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation
7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the
9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions:
10e098bc96SEvan Quan *
11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in
12e098bc96SEvan Quan * all copies or substantial portions of the Software.
13e098bc96SEvan Quan *
14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE.
21e098bc96SEvan Quan *
22e098bc96SEvan Quan */
23e098bc96SEvan Quan
24e098bc96SEvan Quan #include "hwmgr.h"
25e098bc96SEvan Quan #include "vega10_hwmgr.h"
26e098bc96SEvan Quan #include "vega10_smumgr.h"
27e098bc96SEvan Quan #include "vega10_powertune.h"
28e098bc96SEvan Quan #include "vega10_ppsmc.h"
29e098bc96SEvan Quan #include "vega10_inc.h"
30e098bc96SEvan Quan #include "pp_debug.h"
31e098bc96SEvan Quan #include "soc15_common.h"
32e098bc96SEvan Quan
33*223ba213SRan Sun static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] = {
34e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
35e098bc96SEvan Quan * Offset Mask Shift Value
36e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
37e098bc96SEvan Quan */
38e098bc96SEvan Quan /* DIDT_SQ */
39e098bc96SEvan Quan { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853 },
40e098bc96SEvan Quan { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153 },
41e098bc96SEvan Quan
42e098bc96SEvan Quan /* DIDT_TD */
43e098bc96SEvan Quan { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde },
44e098bc96SEvan Quan { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde },
45e098bc96SEvan Quan
46e098bc96SEvan Quan /* DIDT_TCP */
47e098bc96SEvan Quan { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde },
48e098bc96SEvan Quan { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde },
49e098bc96SEvan Quan
50e098bc96SEvan Quan /* DIDT_DB */
51e098bc96SEvan Quan { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde },
52e098bc96SEvan Quan { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde },
53e098bc96SEvan Quan
54e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
55e098bc96SEvan Quan };
56e098bc96SEvan Quan
57*223ba213SRan Sun static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] = {
58e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
59e098bc96SEvan Quan * Offset Mask Shift Value
60e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
61e098bc96SEvan Quan */
62e098bc96SEvan Quan /*DIDT_SQ_CTRL3 */
63e098bc96SEvan Quan { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
64e098bc96SEvan Quan { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
65e098bc96SEvan Quan { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK, DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
66e098bc96SEvan Quan { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
67e098bc96SEvan Quan { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
68e098bc96SEvan Quan { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
69e098bc96SEvan Quan { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
70e098bc96SEvan Quan { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
71e098bc96SEvan Quan { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
72e098bc96SEvan Quan { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK, DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
73e098bc96SEvan Quan { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
74e098bc96SEvan Quan { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
75e098bc96SEvan Quan
76e098bc96SEvan Quan /*DIDT_TCP_CTRL3 */
77e098bc96SEvan Quan { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
78e098bc96SEvan Quan { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
79e098bc96SEvan Quan { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK, DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
80e098bc96SEvan Quan { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
81e098bc96SEvan Quan { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
82e098bc96SEvan Quan { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
83e098bc96SEvan Quan { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
84e098bc96SEvan Quan { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
85e098bc96SEvan Quan { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
86e098bc96SEvan Quan { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
87e098bc96SEvan Quan { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
88e098bc96SEvan Quan { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
89e098bc96SEvan Quan
90e098bc96SEvan Quan /*DIDT_TD_CTRL3 */
91e098bc96SEvan Quan { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
92e098bc96SEvan Quan { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
93e098bc96SEvan Quan { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__THROTTLE_POLICY_MASK, DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
94e098bc96SEvan Quan { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
95e098bc96SEvan Quan { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
96e098bc96SEvan Quan { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
97e098bc96SEvan Quan { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
98e098bc96SEvan Quan { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
99e098bc96SEvan Quan { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
100e098bc96SEvan Quan { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
101e098bc96SEvan Quan { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
102e098bc96SEvan Quan { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
103e098bc96SEvan Quan
104e098bc96SEvan Quan /*DIDT_DB_CTRL3 */
105e098bc96SEvan Quan { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
106e098bc96SEvan Quan { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
107e098bc96SEvan Quan { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__THROTTLE_POLICY_MASK, DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
108e098bc96SEvan Quan { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
109e098bc96SEvan Quan { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
110e098bc96SEvan Quan { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
111e098bc96SEvan Quan { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
112e098bc96SEvan Quan { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
113e098bc96SEvan Quan { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
114e098bc96SEvan Quan { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK, DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
115e098bc96SEvan Quan { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
116e098bc96SEvan Quan { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
117e098bc96SEvan Quan
118e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
119e098bc96SEvan Quan };
120e098bc96SEvan Quan
121*223ba213SRan Sun static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] = {
122e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
123e098bc96SEvan Quan * Offset Mask Shift Value
124e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
125e098bc96SEvan Quan */
126e098bc96SEvan Quan /* DIDT_SQ */
127e098bc96SEvan Quan { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853 },
128e098bc96SEvan Quan { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
129e098bc96SEvan Quan { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000 },
130e098bc96SEvan Quan
131e098bc96SEvan Quan /* DIDT_TD */
132e098bc96SEvan Quan { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff },
133e098bc96SEvan Quan { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
134e098bc96SEvan Quan { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
135e098bc96SEvan Quan
136e098bc96SEvan Quan /* DIDT_TCP */
137e098bc96SEvan Quan { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde },
138e098bc96SEvan Quan { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
139e098bc96SEvan Quan { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
140e098bc96SEvan Quan
141e098bc96SEvan Quan /* DIDT_DB */
142e098bc96SEvan Quan { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK, DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde },
143e098bc96SEvan Quan { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
144e098bc96SEvan Quan { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
145e098bc96SEvan Quan
146e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
147e098bc96SEvan Quan };
148e098bc96SEvan Quan
149*223ba213SRan Sun static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] = {
150e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
151e098bc96SEvan Quan * Offset Mask Shift Value
152e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
153e098bc96SEvan Quan */
154e098bc96SEvan Quan /* DIDT_SQ */
155e098bc96SEvan Quan { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000 },
156e098bc96SEvan Quan { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff },
157e098bc96SEvan Quan /* DIDT_TD */
158e098bc96SEvan Quan { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000 },
159e098bc96SEvan Quan { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff },
160e098bc96SEvan Quan /* DIDT_TCP */
161e098bc96SEvan Quan { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000 },
162e098bc96SEvan Quan { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff },
163e098bc96SEvan Quan /* DIDT_DB */
164e098bc96SEvan Quan { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MIN_POWER_MASK, DIDT_DB_CTRL1__MIN_POWER__SHIFT, 0x0000 },
165e098bc96SEvan Quan { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MAX_POWER_MASK, DIDT_DB_CTRL1__MAX_POWER__SHIFT, 0xffff },
166e098bc96SEvan Quan
167e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
168e098bc96SEvan Quan };
169e098bc96SEvan Quan
170e098bc96SEvan Quan
171*223ba213SRan Sun static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] = {
172e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
173e098bc96SEvan Quan * Offset Mask Shift Value
174e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
175e098bc96SEvan Quan */
176e098bc96SEvan Quan /* DIDT_SQ */
177e098bc96SEvan Quan { ixDIDT_SQ_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B363B1A },
178e098bc96SEvan Quan { ixDIDT_SQ_WEIGHT4_7, 0xFFFFFFFF, 0, 0x270B2432 },
179e098bc96SEvan Quan { ixDIDT_SQ_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000018 },
180e098bc96SEvan Quan
181e098bc96SEvan Quan /* DIDT_TD */
182e098bc96SEvan Quan { ixDIDT_TD_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B1D220F },
183e098bc96SEvan Quan { ixDIDT_TD_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00007558 },
184e098bc96SEvan Quan { ixDIDT_TD_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 },
185e098bc96SEvan Quan
186e098bc96SEvan Quan /* DIDT_TCP */
187e098bc96SEvan Quan { ixDIDT_TCP_WEIGHT0_3, 0xFFFFFFFF, 0, 0x5ACE160D },
188e098bc96SEvan Quan { ixDIDT_TCP_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00000000 },
189e098bc96SEvan Quan { ixDIDT_TCP_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 },
190e098bc96SEvan Quan
191e098bc96SEvan Quan /* DIDT_DB */
192e098bc96SEvan Quan { ixDIDT_DB_WEIGHT0_3, 0xFFFFFFFF, 0, 0x0E152A0F },
193e098bc96SEvan Quan { ixDIDT_DB_WEIGHT4_7, 0xFFFFFFFF, 0, 0x09061813 },
194e098bc96SEvan Quan { ixDIDT_DB_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000013 },
195e098bc96SEvan Quan
196e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
197e098bc96SEvan Quan };
198e098bc96SEvan Quan
199*223ba213SRan Sun static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] = {
200e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
201e098bc96SEvan Quan * Offset Mask Shift Value
202e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
203e098bc96SEvan Quan */
204e098bc96SEvan Quan /* DIDT_SQ */
205e098bc96SEvan Quan { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
206e098bc96SEvan Quan { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
207e098bc96SEvan Quan { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
208e098bc96SEvan Quan { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
209e098bc96SEvan Quan { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
210e098bc96SEvan Quan { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
211e098bc96SEvan Quan { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
212e098bc96SEvan Quan { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
213e098bc96SEvan Quan { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
214e098bc96SEvan Quan { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
215e098bc96SEvan Quan { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
216e098bc96SEvan Quan /* DIDT_TD */
217e098bc96SEvan Quan { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
218e098bc96SEvan Quan { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
219e098bc96SEvan Quan { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
220e098bc96SEvan Quan { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
221e098bc96SEvan Quan { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
222e098bc96SEvan Quan { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
223e098bc96SEvan Quan { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
224e098bc96SEvan Quan { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
225e098bc96SEvan Quan { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
226e098bc96SEvan Quan { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
227e098bc96SEvan Quan { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
228e098bc96SEvan Quan /* DIDT_TCP */
229e098bc96SEvan Quan { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
230e098bc96SEvan Quan { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
231e098bc96SEvan Quan { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
232e098bc96SEvan Quan { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
233e098bc96SEvan Quan { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
234e098bc96SEvan Quan { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
235e098bc96SEvan Quan { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
236e098bc96SEvan Quan { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
237e098bc96SEvan Quan { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
238e098bc96SEvan Quan { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
239e098bc96SEvan Quan { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
240e098bc96SEvan Quan /* DIDT_DB */
241e098bc96SEvan Quan { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
242e098bc96SEvan Quan { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__PHASE_OFFSET_MASK, DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
243e098bc96SEvan Quan { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK, DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
244e098bc96SEvan Quan { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
245e098bc96SEvan Quan { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
246e098bc96SEvan Quan { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
247e098bc96SEvan Quan { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
248e098bc96SEvan Quan { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
249e098bc96SEvan Quan { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
250e098bc96SEvan Quan { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
251e098bc96SEvan Quan { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
252e098bc96SEvan Quan
253e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
254e098bc96SEvan Quan };
255e098bc96SEvan Quan
256e098bc96SEvan Quan
257*223ba213SRan Sun static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] = {
258e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
259e098bc96SEvan Quan * Offset Mask Shift Value
260e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
261e098bc96SEvan Quan */
262e098bc96SEvan Quan /* DIDT_SQ */
263e098bc96SEvan Quan { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 },
264e098bc96SEvan Quan { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 },
265e098bc96SEvan Quan { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
266e098bc96SEvan Quan { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
267e098bc96SEvan Quan
268e098bc96SEvan Quan /* DIDT_TD */
269e098bc96SEvan Quan { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 },
270e098bc96SEvan Quan { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 },
271e098bc96SEvan Quan { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
272e098bc96SEvan Quan { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
273e098bc96SEvan Quan
274e098bc96SEvan Quan /* DIDT_TCP */
275e098bc96SEvan Quan { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 },
276e098bc96SEvan Quan { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 },
277e098bc96SEvan Quan { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
278e098bc96SEvan Quan { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
279e098bc96SEvan Quan
280e098bc96SEvan Quan /* DIDT_DB */
281e098bc96SEvan Quan { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 },
282e098bc96SEvan Quan { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 },
283e098bc96SEvan Quan { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
284e098bc96SEvan Quan { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
285e098bc96SEvan Quan
286e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
287e098bc96SEvan Quan };
288e098bc96SEvan Quan
289*223ba213SRan Sun static const struct vega10_didt_config_reg SEDiDtStallPatternConfig_vega10[] = {
290e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
291e098bc96SEvan Quan * Offset Mask Shift Value
292e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
293e098bc96SEvan Quan */
294e098bc96SEvan Quan /* DIDT_SQ_STALL_PATTERN_1_2 */
295e098bc96SEvan Quan { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
296e098bc96SEvan Quan { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
297e098bc96SEvan Quan
298e098bc96SEvan Quan /* DIDT_SQ_STALL_PATTERN_3_4 */
299e098bc96SEvan Quan { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
300e098bc96SEvan Quan { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
301e098bc96SEvan Quan
302e098bc96SEvan Quan /* DIDT_SQ_STALL_PATTERN_5_6 */
303e098bc96SEvan Quan { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
304e098bc96SEvan Quan { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
305e098bc96SEvan Quan
306e098bc96SEvan Quan /* DIDT_SQ_STALL_PATTERN_7 */
307e098bc96SEvan Quan { ixDIDT_SQ_STALL_PATTERN_7, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
308e098bc96SEvan Quan
309e098bc96SEvan Quan /* DIDT_TCP_STALL_PATTERN_1_2 */
310e098bc96SEvan Quan { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
311e098bc96SEvan Quan { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
312e098bc96SEvan Quan
313e098bc96SEvan Quan /* DIDT_TCP_STALL_PATTERN_3_4 */
314e098bc96SEvan Quan { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
315e098bc96SEvan Quan { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
316e098bc96SEvan Quan
317e098bc96SEvan Quan /* DIDT_TCP_STALL_PATTERN_5_6 */
318e098bc96SEvan Quan { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
319e098bc96SEvan Quan { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
320e098bc96SEvan Quan
321e098bc96SEvan Quan /* DIDT_TCP_STALL_PATTERN_7 */
322e098bc96SEvan Quan { ixDIDT_TCP_STALL_PATTERN_7, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
323e098bc96SEvan Quan
324e098bc96SEvan Quan /* DIDT_TD_STALL_PATTERN_1_2 */
325e098bc96SEvan Quan { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
326e098bc96SEvan Quan { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
327e098bc96SEvan Quan
328e098bc96SEvan Quan /* DIDT_TD_STALL_PATTERN_3_4 */
329e098bc96SEvan Quan { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
330e098bc96SEvan Quan { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
331e098bc96SEvan Quan
332e098bc96SEvan Quan /* DIDT_TD_STALL_PATTERN_5_6 */
333e098bc96SEvan Quan { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
334e098bc96SEvan Quan { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
335e098bc96SEvan Quan
336e098bc96SEvan Quan /* DIDT_TD_STALL_PATTERN_7 */
337e098bc96SEvan Quan { ixDIDT_TD_STALL_PATTERN_7, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
338e098bc96SEvan Quan
339e098bc96SEvan Quan /* DIDT_DB_STALL_PATTERN_1_2 */
340e098bc96SEvan Quan { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
341e098bc96SEvan Quan { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
342e098bc96SEvan Quan
343e098bc96SEvan Quan /* DIDT_DB_STALL_PATTERN_3_4 */
344e098bc96SEvan Quan { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
345e098bc96SEvan Quan { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
346e098bc96SEvan Quan
347e098bc96SEvan Quan /* DIDT_DB_STALL_PATTERN_5_6 */
348e098bc96SEvan Quan { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
349e098bc96SEvan Quan { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
350e098bc96SEvan Quan
351e098bc96SEvan Quan /* DIDT_DB_STALL_PATTERN_7 */
352e098bc96SEvan Quan { ixDIDT_DB_STALL_PATTERN_7, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
353e098bc96SEvan Quan
354e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
355e098bc96SEvan Quan };
356e098bc96SEvan Quan
357*223ba213SRan Sun static const struct vega10_didt_config_reg SELCacConfig_Vega10[] = {
358e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
359e098bc96SEvan Quan * Offset Mask Shift Value
360e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
361e098bc96SEvan Quan */
362e098bc96SEvan Quan /* SQ */
363e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060021 },
364e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860021 },
365e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060021 },
366e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860021 },
367e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060021 },
368e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860021 },
369e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060021 },
370e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860021 },
371e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060021 },
372e098bc96SEvan Quan /* TD */
373e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0020 },
374e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0020 },
375e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0020 },
376e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0020 },
377e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0020 },
378e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x028E0020 },
379e098bc96SEvan Quan /* TCP */
380e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x001c0020 },
381e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x009c0020 },
382e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x011c0020 },
383e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x019c0020 },
384e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x021c0020 },
385e098bc96SEvan Quan /* DB */
386e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00200008 },
387e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00820008 },
388e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01020008 },
389e098bc96SEvan Quan { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01820008 },
390e098bc96SEvan Quan
391e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
392e098bc96SEvan Quan };
393e098bc96SEvan Quan
394e098bc96SEvan Quan
395*223ba213SRan Sun static const struct vega10_didt_config_reg SEEDCStallPatternConfig_Vega10[] = {
396e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
397e098bc96SEvan Quan * Offset Mask Shift Value
398e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
399e098bc96SEvan Quan */
400e098bc96SEvan Quan /* SQ */
401e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00030001 },
402e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x000F0007 },
403e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x003F001F },
404e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x0000007F },
405e098bc96SEvan Quan /* TD */
406e098bc96SEvan Quan { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 },
407e098bc96SEvan Quan { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
408e098bc96SEvan Quan { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
409e098bc96SEvan Quan { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
410e098bc96SEvan Quan /* TCP */
411e098bc96SEvan Quan { ixDIDT_TCP_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 },
412e098bc96SEvan Quan { ixDIDT_TCP_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
413e098bc96SEvan Quan { ixDIDT_TCP_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
414e098bc96SEvan Quan { ixDIDT_TCP_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
415e098bc96SEvan Quan /* DB */
416e098bc96SEvan Quan { ixDIDT_DB_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 },
417e098bc96SEvan Quan { ixDIDT_DB_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
418e098bc96SEvan Quan { ixDIDT_DB_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
419e098bc96SEvan Quan { ixDIDT_DB_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
420e098bc96SEvan Quan
421e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
422e098bc96SEvan Quan };
423e098bc96SEvan Quan
424*223ba213SRan Sun static const struct vega10_didt_config_reg SEEDCForceStallPatternConfig_Vega10[] = {
425e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
426e098bc96SEvan Quan * Offset Mask Shift Value
427e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
428e098bc96SEvan Quan */
429e098bc96SEvan Quan /* SQ */
430e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 },
431e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
432e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
433e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
434e098bc96SEvan Quan /* TD */
435e098bc96SEvan Quan { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 },
436e098bc96SEvan Quan { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
437e098bc96SEvan Quan { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
438e098bc96SEvan Quan { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
439e098bc96SEvan Quan
440e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
441e098bc96SEvan Quan };
442e098bc96SEvan Quan
443*223ba213SRan Sun static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] = {
444e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
445e098bc96SEvan Quan * Offset Mask Shift Value
446e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
447e098bc96SEvan Quan */
448e098bc96SEvan Quan /* SQ */
449e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
450e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 },
451e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 },
452e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 },
453e098bc96SEvan Quan /* TD */
454e098bc96SEvan Quan { ixDIDT_TD_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
455e098bc96SEvan Quan { ixDIDT_TD_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 },
456e098bc96SEvan Quan { ixDIDT_TD_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 },
457e098bc96SEvan Quan { ixDIDT_TD_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 },
458e098bc96SEvan Quan /* TCP */
459e098bc96SEvan Quan { ixDIDT_TCP_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
460e098bc96SEvan Quan { ixDIDT_TCP_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 },
461e098bc96SEvan Quan { ixDIDT_TCP_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 },
462e098bc96SEvan Quan { ixDIDT_TCP_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 },
463e098bc96SEvan Quan /* DB */
464e098bc96SEvan Quan { ixDIDT_DB_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
465e098bc96SEvan Quan
466e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
467e098bc96SEvan Quan };
468e098bc96SEvan Quan
469*223ba213SRan Sun static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] = {
470e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
471e098bc96SEvan Quan * Offset Mask Shift Value
472e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
473e098bc96SEvan Quan */
474e098bc96SEvan Quan { ixDIDT_SQ_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0x0000010E },
475e098bc96SEvan Quan { ixDIDT_TD_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF },
476e098bc96SEvan Quan { ixDIDT_TCP_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF },
477e098bc96SEvan Quan { ixDIDT_DB_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF },
478e098bc96SEvan Quan
479e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
480e098bc96SEvan Quan };
481e098bc96SEvan Quan
482*223ba213SRan Sun static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] = {
483e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
484e098bc96SEvan Quan * Offset Mask Shift Value
485e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
486e098bc96SEvan Quan */
487e098bc96SEvan Quan /* SQ */
488e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
489e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
490e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
491e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
492e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
493e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 },
494e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
495e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
496e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
497e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
498e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
499e098bc96SEvan Quan
500e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
501e098bc96SEvan Quan };
502e098bc96SEvan Quan
503*223ba213SRan Sun static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] = {
504e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
505e098bc96SEvan Quan * Offset Mask Shift Value
506e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
507e098bc96SEvan Quan */
508e098bc96SEvan Quan /* SQ */
509e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
510e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
511e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
512e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
513e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0004 },
514e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0006 },
515e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
516e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
517e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
518e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
519e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
520e098bc96SEvan Quan
521e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
522e098bc96SEvan Quan };
523e098bc96SEvan Quan
524*223ba213SRan Sun static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] = {
525e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
526e098bc96SEvan Quan * Offset Mask Shift Value
527e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
528e098bc96SEvan Quan */
529e098bc96SEvan Quan /* SQ */
530e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
531e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
532e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
533e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 },
534e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 },
535e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000C },
536e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
537e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
538e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
539e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
540e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
541e098bc96SEvan Quan
542e098bc96SEvan Quan /* TD */
543e098bc96SEvan Quan { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_EN_MASK, DIDT_TD_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
544e098bc96SEvan Quan { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK, DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
545e098bc96SEvan Quan { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
546e098bc96SEvan Quan { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 },
547e098bc96SEvan Quan { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 },
548e098bc96SEvan Quan { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E },
549e098bc96SEvan Quan { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
550e098bc96SEvan Quan { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
551e098bc96SEvan Quan { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
552e098bc96SEvan Quan { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
553e098bc96SEvan Quan { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
554e098bc96SEvan Quan
555e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
556e098bc96SEvan Quan };
557e098bc96SEvan Quan
558*223ba213SRan Sun static const struct vega10_didt_config_reg GCDiDtDroopCtrlConfig_vega10[] = {
559e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
560e098bc96SEvan Quan * Offset Mask Shift Value
561e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
562e098bc96SEvan Quan */
563e098bc96SEvan Quan { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT, 0x0000 },
564e098bc96SEvan Quan { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT, 0x0000 },
565e098bc96SEvan Quan { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT, 0x0000 },
566e098bc96SEvan Quan { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT, 0x0000 },
567e098bc96SEvan Quan { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT, 0x0000 },
568e098bc96SEvan Quan
569e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
570e098bc96SEvan Quan };
571e098bc96SEvan Quan
572*223ba213SRan Sun static const struct vega10_didt_config_reg GCDiDtCtrl0Config_vega10[] = {
573e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
574e098bc96SEvan Quan * Offset Mask Shift Value
575e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
576e098bc96SEvan Quan */
577e098bc96SEvan Quan { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK, GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
578e098bc96SEvan Quan { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__PHASE_OFFSET_MASK, GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
579e098bc96SEvan Quan { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_SW_RST_MASK, GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT, 0x0000 },
580e098bc96SEvan Quan { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
581e098bc96SEvan Quan { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
582e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
583e098bc96SEvan Quan };
584e098bc96SEvan Quan
585e098bc96SEvan Quan
586*223ba213SRan Sun static const struct vega10_didt_config_reg PSMSEEDCStallPatternConfig_Vega10[] = {
587e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
588e098bc96SEvan Quan * Offset Mask Shift Value
589e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
590e098bc96SEvan Quan */
591e098bc96SEvan Quan /* SQ EDC STALL PATTERNs */
592e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT, 0x0101 },
593e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT, 0x0101 },
594e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT, 0x1111 },
595e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT, 0x1111 },
596e098bc96SEvan Quan
597e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT, 0x1515 },
598e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT, 0x1515 },
599e098bc96SEvan Quan
600e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_PATTERN_7, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT, 0x5555 },
601e098bc96SEvan Quan
602e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
603e098bc96SEvan Quan };
604e098bc96SEvan Quan
605*223ba213SRan Sun static const struct vega10_didt_config_reg PSMSEEDCStallDelayConfig_Vega10[] = {
606e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
607e098bc96SEvan Quan * Offset Mask Shift Value
608e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
609e098bc96SEvan Quan */
610e098bc96SEvan Quan /* SQ EDC STALL DELAYs */
611e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT, 0x0000 },
612e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT, 0x0000 },
613e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT, 0x0000 },
614e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT, 0x0000 },
615e098bc96SEvan Quan
616e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT, 0x0000 },
617e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT, 0x0000 },
618e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT, 0x0000 },
619e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT, 0x0000 },
620e098bc96SEvan Quan
621e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT, 0x0000 },
622e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT, 0x0000 },
623e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT, 0x0000 },
624e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT, 0x0000 },
625e098bc96SEvan Quan
626e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT, 0x0000 },
627e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT, 0x0000 },
628e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT, 0x0000 },
629e098bc96SEvan Quan { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT, 0x0000 },
630e098bc96SEvan Quan
631e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
632e098bc96SEvan Quan };
633e098bc96SEvan Quan
634*223ba213SRan Sun static const struct vega10_didt_config_reg PSMSEEDCCtrlResetConfig_Vega10[] = {
635e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
636e098bc96SEvan Quan * Offset Mask Shift Value
637e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
638e098bc96SEvan Quan */
639e098bc96SEvan Quan /* SQ EDC CTRL */
640e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
641e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
642e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
643e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
644e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
645e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 },
646e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
647e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
648e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
649e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
650e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
651e098bc96SEvan Quan
652e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
653e098bc96SEvan Quan };
654e098bc96SEvan Quan
655*223ba213SRan Sun static const struct vega10_didt_config_reg PSMSEEDCCtrlConfig_Vega10[] = {
656e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
657e098bc96SEvan Quan * Offset Mask Shift Value
658e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
659e098bc96SEvan Quan */
660e098bc96SEvan Quan /* SQ EDC CTRL */
661e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
662e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
663e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
664e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
665e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
666e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E },
667e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
668e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0001 },
669e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0003 },
670e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
671e098bc96SEvan Quan { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
672e098bc96SEvan Quan
673e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
674e098bc96SEvan Quan };
675e098bc96SEvan Quan
676*223ba213SRan Sun static const struct vega10_didt_config_reg PSMGCEDCDroopCtrlConfig_vega10[] = {
677e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
678e098bc96SEvan Quan * Offset Mask Shift Value
679e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
680e098bc96SEvan Quan */
681e098bc96SEvan Quan { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT, 0x0001 },
682e098bc96SEvan Quan { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT, 0x0384 },
683e098bc96SEvan Quan { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT, 0x0001 },
684e098bc96SEvan Quan { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK, GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT, 0x0001 },
685e098bc96SEvan Quan { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT, 0x0001 },
686e098bc96SEvan Quan
687e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
688e098bc96SEvan Quan };
689e098bc96SEvan Quan
690*223ba213SRan Sun static const struct vega10_didt_config_reg PSMGCEDCCtrlResetConfig_vega10[] = {
691e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
692e098bc96SEvan Quan * Offset Mask Shift Value
693e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
694e098bc96SEvan Quan */
695e098bc96SEvan Quan { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
696e098bc96SEvan Quan { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
697e098bc96SEvan Quan { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
698e098bc96SEvan Quan { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
699e098bc96SEvan Quan { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
700e098bc96SEvan Quan { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
701e098bc96SEvan Quan
702e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
703e098bc96SEvan Quan };
704e098bc96SEvan Quan
705*223ba213SRan Sun static const struct vega10_didt_config_reg PSMGCEDCCtrlConfig_vega10[] = {
706e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
707e098bc96SEvan Quan * Offset Mask Shift Value
708e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
709e098bc96SEvan Quan */
710e098bc96SEvan Quan { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
711e098bc96SEvan Quan { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
712e098bc96SEvan Quan { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
713e098bc96SEvan Quan { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
714e098bc96SEvan Quan { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
715e098bc96SEvan Quan { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
716e098bc96SEvan Quan
717e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
718e098bc96SEvan Quan };
719e098bc96SEvan Quan
720*223ba213SRan Sun static const struct vega10_didt_config_reg AvfsPSMResetConfig_vega10[] = {
721e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
722e098bc96SEvan Quan * Offset Mask Shift Value
723e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
724e098bc96SEvan Quan */
725e098bc96SEvan Quan { 0x16A02, 0xFFFFFFFF, 0x0, 0x0000005F },
726e098bc96SEvan Quan { 0x16A05, 0xFFFFFFFF, 0x0, 0x00000001 },
727e098bc96SEvan Quan { 0x16A06, 0x00000001, 0x0, 0x02000000 },
728e098bc96SEvan Quan { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 },
729e098bc96SEvan Quan
730e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
731e098bc96SEvan Quan };
732e098bc96SEvan Quan
733*223ba213SRan Sun static const struct vega10_didt_config_reg AvfsPSMInitConfig_vega10[] = {
734e098bc96SEvan Quan /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
735e098bc96SEvan Quan * Offset Mask Shift Value
736e098bc96SEvan Quan * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
737e098bc96SEvan Quan */
738e098bc96SEvan Quan { 0x16A05, 0xFFFFFFFF, 0x18, 0x00000001 },
739e098bc96SEvan Quan { 0x16A05, 0xFFFFFFFF, 0x8, 0x00000003 },
740e098bc96SEvan Quan { 0x16A05, 0xFFFFFFFF, 0xa, 0x00000006 },
741e098bc96SEvan Quan { 0x16A05, 0xFFFFFFFF, 0x7, 0x00000000 },
742e098bc96SEvan Quan { 0x16A06, 0xFFFFFFFF, 0x18, 0x00000001 },
743e098bc96SEvan Quan { 0x16A06, 0xFFFFFFFF, 0x19, 0x00000001 },
744e098bc96SEvan Quan { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 },
745e098bc96SEvan Quan
746e098bc96SEvan Quan { 0xFFFFFFFF } /* End of list */
747e098bc96SEvan Quan };
748e098bc96SEvan Quan
vega10_program_didt_config_registers(struct pp_hwmgr * hwmgr,const struct vega10_didt_config_reg * config_regs,enum vega10_didt_config_reg_type reg_type)749e098bc96SEvan Quan static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs, enum vega10_didt_config_reg_type reg_type)
750e098bc96SEvan Quan {
751e098bc96SEvan Quan uint32_t data;
752e098bc96SEvan Quan
753e098bc96SEvan Quan PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL);
754e098bc96SEvan Quan
755e098bc96SEvan Quan while (config_regs->offset != 0xFFFFFFFF) {
756e098bc96SEvan Quan switch (reg_type) {
757e098bc96SEvan Quan case VEGA10_CONFIGREG_DIDT:
758e098bc96SEvan Quan data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
759e098bc96SEvan Quan data &= ~config_regs->mask;
760e098bc96SEvan Quan data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
761e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
762e098bc96SEvan Quan break;
763e098bc96SEvan Quan case VEGA10_CONFIGREG_GCCAC:
764e098bc96SEvan Quan data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
765e098bc96SEvan Quan data &= ~config_regs->mask;
766e098bc96SEvan Quan data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
767e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
768e098bc96SEvan Quan break;
769e098bc96SEvan Quan case VEGA10_CONFIGREG_SECAC:
770e098bc96SEvan Quan data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset);
771e098bc96SEvan Quan data &= ~config_regs->mask;
772e098bc96SEvan Quan data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
773e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data);
774e098bc96SEvan Quan break;
775e098bc96SEvan Quan default:
776e098bc96SEvan Quan return -EINVAL;
777e098bc96SEvan Quan }
778e098bc96SEvan Quan
779e098bc96SEvan Quan config_regs++;
780e098bc96SEvan Quan }
781e098bc96SEvan Quan
782e098bc96SEvan Quan return 0;
783e098bc96SEvan Quan }
784e098bc96SEvan Quan
vega10_program_gc_didt_config_registers(struct pp_hwmgr * hwmgr,const struct vega10_didt_config_reg * config_regs)785e098bc96SEvan Quan static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs)
786e098bc96SEvan Quan {
787e098bc96SEvan Quan uint32_t data;
788e098bc96SEvan Quan
789e098bc96SEvan Quan while (config_regs->offset != 0xFFFFFFFF) {
790e098bc96SEvan Quan data = cgs_read_register(hwmgr->device, config_regs->offset);
791e098bc96SEvan Quan data &= ~config_regs->mask;
792e098bc96SEvan Quan data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
793e098bc96SEvan Quan cgs_write_register(hwmgr->device, config_regs->offset, data);
794e098bc96SEvan Quan config_regs++;
795e098bc96SEvan Quan }
796e098bc96SEvan Quan
797e098bc96SEvan Quan return 0;
798e098bc96SEvan Quan }
799e098bc96SEvan Quan
vega10_didt_set_mask(struct pp_hwmgr * hwmgr,const bool enable)800e098bc96SEvan Quan static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
801e098bc96SEvan Quan {
802e098bc96SEvan Quan uint32_t data;
803e098bc96SEvan Quan uint32_t en = (enable ? 1 : 0);
804e098bc96SEvan Quan uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
805e098bc96SEvan Quan
806e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
807e098bc96SEvan Quan CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
808e098bc96SEvan Quan DIDT_SQ_CTRL0, DIDT_CTRL_EN, en);
809e098bc96SEvan Quan didt_block_info &= ~SQ_Enable_MASK;
810e098bc96SEvan Quan didt_block_info |= en << SQ_Enable_SHIFT;
811e098bc96SEvan Quan }
812e098bc96SEvan Quan
813e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
814e098bc96SEvan Quan CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
815e098bc96SEvan Quan DIDT_DB_CTRL0, DIDT_CTRL_EN, en);
816e098bc96SEvan Quan didt_block_info &= ~DB_Enable_MASK;
817e098bc96SEvan Quan didt_block_info |= en << DB_Enable_SHIFT;
818e098bc96SEvan Quan }
819e098bc96SEvan Quan
820e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
821e098bc96SEvan Quan CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
822e098bc96SEvan Quan DIDT_TD_CTRL0, DIDT_CTRL_EN, en);
823e098bc96SEvan Quan didt_block_info &= ~TD_Enable_MASK;
824e098bc96SEvan Quan didt_block_info |= en << TD_Enable_SHIFT;
825e098bc96SEvan Quan }
826e098bc96SEvan Quan
827e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
828e098bc96SEvan Quan CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
829e098bc96SEvan Quan DIDT_TCP_CTRL0, DIDT_CTRL_EN, en);
830e098bc96SEvan Quan didt_block_info &= ~TCP_Enable_MASK;
831e098bc96SEvan Quan didt_block_info |= en << TCP_Enable_SHIFT;
832e098bc96SEvan Quan }
833e098bc96SEvan Quan
834e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
835e098bc96SEvan Quan CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
836e098bc96SEvan Quan DIDT_DBR_CTRL0, DIDT_CTRL_EN, en);
837e098bc96SEvan Quan }
838e098bc96SEvan Quan
839e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) {
840e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
841e098bc96SEvan Quan data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
842e098bc96SEvan Quan data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
843e098bc96SEvan Quan data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
844e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);
845e098bc96SEvan Quan }
846e098bc96SEvan Quan
847e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
848e098bc96SEvan Quan data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
849e098bc96SEvan Quan data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
850e098bc96SEvan Quan data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
851e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);
852e098bc96SEvan Quan }
853e098bc96SEvan Quan
854e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
855e098bc96SEvan Quan data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
856e098bc96SEvan Quan data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
857e098bc96SEvan Quan data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
858e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);
859e098bc96SEvan Quan }
860e098bc96SEvan Quan
861e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
862e098bc96SEvan Quan data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
863e098bc96SEvan Quan data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
864e098bc96SEvan Quan data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
865e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);
866e098bc96SEvan Quan }
867e098bc96SEvan Quan
868e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
869e098bc96SEvan Quan data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
870e098bc96SEvan Quan data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
871e098bc96SEvan Quan data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
872e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);
873e098bc96SEvan Quan }
874e098bc96SEvan Quan }
875e098bc96SEvan Quan
876e098bc96SEvan Quan /* For Vega10, SMC does not support any mask yet. */
877e098bc96SEvan Quan if (enable)
878e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info,
879e098bc96SEvan Quan NULL);
880e098bc96SEvan Quan
881e098bc96SEvan Quan }
882e098bc96SEvan Quan
vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr * hwmgr)883e098bc96SEvan Quan static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
884e098bc96SEvan Quan {
885e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
886e098bc96SEvan Quan int result;
887e098bc96SEvan Quan uint32_t num_se = 0, count, data;
888e098bc96SEvan Quan
889e098bc96SEvan Quan num_se = adev->gfx.config.max_shader_engines;
890e098bc96SEvan Quan
89186b20703SLe Ma amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
892e098bc96SEvan Quan
893e098bc96SEvan Quan mutex_lock(&adev->grbm_idx_mutex);
894e098bc96SEvan Quan for (count = 0; count < num_se; count++) {
895e098bc96SEvan Quan data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
896e098bc96SEvan Quan WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
897e098bc96SEvan Quan
898e098bc96SEvan Quan result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
899e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
900e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
901e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl1Config_Vega10, VEGA10_CONFIGREG_DIDT);
902e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl2Config_Vega10, VEGA10_CONFIGREG_DIDT);
903e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
904e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEDiDtTuningCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
905e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SELCacConfig_Vega10, VEGA10_CONFIGREG_SECAC);
906e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
907e098bc96SEvan Quan
908e098bc96SEvan Quan if (0 != result)
909e098bc96SEvan Quan break;
910e098bc96SEvan Quan }
911e098bc96SEvan Quan WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
912e098bc96SEvan Quan mutex_unlock(&adev->grbm_idx_mutex);
913e098bc96SEvan Quan
914e098bc96SEvan Quan vega10_didt_set_mask(hwmgr, true);
915e098bc96SEvan Quan
91686b20703SLe Ma amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
917e098bc96SEvan Quan
918e098bc96SEvan Quan return 0;
919e098bc96SEvan Quan }
920e098bc96SEvan Quan
vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr * hwmgr)921e098bc96SEvan Quan static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
922e098bc96SEvan Quan {
923e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
924e098bc96SEvan Quan
92586b20703SLe Ma amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
926e098bc96SEvan Quan
927e098bc96SEvan Quan vega10_didt_set_mask(hwmgr, false);
928e098bc96SEvan Quan
92986b20703SLe Ma amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
930e098bc96SEvan Quan
931e098bc96SEvan Quan return 0;
932e098bc96SEvan Quan }
933e098bc96SEvan Quan
vega10_enable_psm_gc_didt_config(struct pp_hwmgr * hwmgr)934e098bc96SEvan Quan static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
935e098bc96SEvan Quan {
936e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
937e098bc96SEvan Quan int result;
938e098bc96SEvan Quan uint32_t num_se = 0, count, data;
939e098bc96SEvan Quan
940e098bc96SEvan Quan num_se = adev->gfx.config.max_shader_engines;
941e098bc96SEvan Quan
94286b20703SLe Ma amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
943e098bc96SEvan Quan
944e098bc96SEvan Quan mutex_lock(&adev->grbm_idx_mutex);
945e098bc96SEvan Quan for (count = 0; count < num_se; count++) {
946e098bc96SEvan Quan data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
947e098bc96SEvan Quan WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
948e098bc96SEvan Quan
949e098bc96SEvan Quan result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
950e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
951e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
952e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
953e098bc96SEvan Quan if (0 != result)
954e098bc96SEvan Quan break;
955e098bc96SEvan Quan }
956e098bc96SEvan Quan WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
957e098bc96SEvan Quan mutex_unlock(&adev->grbm_idx_mutex);
958e098bc96SEvan Quan
959e098bc96SEvan Quan vega10_didt_set_mask(hwmgr, true);
960e098bc96SEvan Quan
96186b20703SLe Ma amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
962e098bc96SEvan Quan
963e098bc96SEvan Quan vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10);
964e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_GCEDC))
965e098bc96SEvan Quan vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10);
966e098bc96SEvan Quan
967e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_PSM))
968e098bc96SEvan Quan vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
969e098bc96SEvan Quan
970e098bc96SEvan Quan return 0;
971e098bc96SEvan Quan }
972e098bc96SEvan Quan
vega10_disable_psm_gc_didt_config(struct pp_hwmgr * hwmgr)973e098bc96SEvan Quan static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
974e098bc96SEvan Quan {
975e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
976e098bc96SEvan Quan uint32_t data;
977e098bc96SEvan Quan
97886b20703SLe Ma amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
979e098bc96SEvan Quan
980e098bc96SEvan Quan vega10_didt_set_mask(hwmgr, false);
981e098bc96SEvan Quan
98286b20703SLe Ma amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
983e098bc96SEvan Quan
984e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
985e098bc96SEvan Quan data = 0x00000000;
986e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data);
987e098bc96SEvan Quan }
988e098bc96SEvan Quan
989e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_PSM))
990e098bc96SEvan Quan vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
991e098bc96SEvan Quan
992e098bc96SEvan Quan return 0;
993e098bc96SEvan Quan }
994e098bc96SEvan Quan
vega10_enable_se_edc_config(struct pp_hwmgr * hwmgr)995e098bc96SEvan Quan static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
996e098bc96SEvan Quan {
997e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
998e098bc96SEvan Quan int result;
999e098bc96SEvan Quan uint32_t num_se = 0, count, data;
1000e098bc96SEvan Quan
1001e098bc96SEvan Quan num_se = adev->gfx.config.max_shader_engines;
1002e098bc96SEvan Quan
100386b20703SLe Ma amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1004e098bc96SEvan Quan
1005e098bc96SEvan Quan mutex_lock(&adev->grbm_idx_mutex);
1006e098bc96SEvan Quan for (count = 0; count < num_se; count++) {
1007e098bc96SEvan Quan data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1008e098bc96SEvan Quan WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1009e098bc96SEvan Quan result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1010e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1011e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1012e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEEDCThresholdConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1013e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1014e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1015e098bc96SEvan Quan
1016e098bc96SEvan Quan if (0 != result)
1017e098bc96SEvan Quan break;
1018e098bc96SEvan Quan }
1019e098bc96SEvan Quan WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1020e098bc96SEvan Quan mutex_unlock(&adev->grbm_idx_mutex);
1021e098bc96SEvan Quan
1022e098bc96SEvan Quan vega10_didt_set_mask(hwmgr, true);
1023e098bc96SEvan Quan
102486b20703SLe Ma amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1025e098bc96SEvan Quan
1026e098bc96SEvan Quan return 0;
1027e098bc96SEvan Quan }
1028e098bc96SEvan Quan
vega10_disable_se_edc_config(struct pp_hwmgr * hwmgr)1029e098bc96SEvan Quan static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr)
1030e098bc96SEvan Quan {
1031e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
1032e098bc96SEvan Quan
103386b20703SLe Ma amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1034e098bc96SEvan Quan
1035e098bc96SEvan Quan vega10_didt_set_mask(hwmgr, false);
1036e098bc96SEvan Quan
103786b20703SLe Ma amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1038e098bc96SEvan Quan
1039e098bc96SEvan Quan return 0;
1040e098bc96SEvan Quan }
1041e098bc96SEvan Quan
vega10_enable_psm_gc_edc_config(struct pp_hwmgr * hwmgr)1042e098bc96SEvan Quan static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
1043e098bc96SEvan Quan {
1044e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
1045e098bc96SEvan Quan int result = 0;
1046e098bc96SEvan Quan uint32_t num_se = 0;
1047e098bc96SEvan Quan uint32_t count, data;
1048e098bc96SEvan Quan
1049e098bc96SEvan Quan num_se = adev->gfx.config.max_shader_engines;
1050e098bc96SEvan Quan
105186b20703SLe Ma amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1052e098bc96SEvan Quan
1053e098bc96SEvan Quan vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
1054e098bc96SEvan Quan
1055e098bc96SEvan Quan mutex_lock(&adev->grbm_idx_mutex);
1056e098bc96SEvan Quan for (count = 0; count < num_se; count++) {
1057e098bc96SEvan Quan data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1058e098bc96SEvan Quan WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1059e098bc96SEvan Quan result = vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1060e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1061e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1062e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1063e098bc96SEvan Quan
1064e098bc96SEvan Quan if (0 != result)
1065e098bc96SEvan Quan break;
1066e098bc96SEvan Quan }
1067e098bc96SEvan Quan WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1068e098bc96SEvan Quan mutex_unlock(&adev->grbm_idx_mutex);
1069e098bc96SEvan Quan
1070e098bc96SEvan Quan vega10_didt_set_mask(hwmgr, true);
1071e098bc96SEvan Quan
107286b20703SLe Ma amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1073e098bc96SEvan Quan
1074e098bc96SEvan Quan vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10);
1075e098bc96SEvan Quan
1076e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1077e098bc96SEvan Quan vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10);
1078e098bc96SEvan Quan vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10);
1079e098bc96SEvan Quan }
1080e098bc96SEvan Quan
1081e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_PSM))
1082e098bc96SEvan Quan vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
1083e098bc96SEvan Quan
1084e098bc96SEvan Quan return 0;
1085e098bc96SEvan Quan }
1086e098bc96SEvan Quan
vega10_disable_psm_gc_edc_config(struct pp_hwmgr * hwmgr)1087e098bc96SEvan Quan static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
1088e098bc96SEvan Quan {
1089e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
1090e098bc96SEvan Quan uint32_t data;
1091e098bc96SEvan Quan
109286b20703SLe Ma amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1093e098bc96SEvan Quan
1094e098bc96SEvan Quan vega10_didt_set_mask(hwmgr, false);
1095e098bc96SEvan Quan
109686b20703SLe Ma amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1097e098bc96SEvan Quan
1098e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1099e098bc96SEvan Quan data = 0x00000000;
1100e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
1101e098bc96SEvan Quan }
1102e098bc96SEvan Quan
1103e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_PSM))
1104e098bc96SEvan Quan vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
1105e098bc96SEvan Quan
1106e098bc96SEvan Quan return 0;
1107e098bc96SEvan Quan }
1108e098bc96SEvan Quan
vega10_enable_se_edc_force_stall_config(struct pp_hwmgr * hwmgr)1109e098bc96SEvan Quan static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
1110e098bc96SEvan Quan {
1111e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
1112e098bc96SEvan Quan int result;
1113e098bc96SEvan Quan
111486b20703SLe Ma amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1115e098bc96SEvan Quan
1116e098bc96SEvan Quan mutex_lock(&adev->grbm_idx_mutex);
1117e098bc96SEvan Quan WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1118e098bc96SEvan Quan mutex_unlock(&adev->grbm_idx_mutex);
1119e098bc96SEvan Quan
1120e098bc96SEvan Quan result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1121e098bc96SEvan Quan result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1122e098bc96SEvan Quan if (0 != result)
1123e098bc96SEvan Quan return result;
1124e098bc96SEvan Quan
1125e098bc96SEvan Quan vega10_didt_set_mask(hwmgr, false);
1126e098bc96SEvan Quan
112786b20703SLe Ma amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1128e098bc96SEvan Quan
1129e098bc96SEvan Quan return 0;
1130e098bc96SEvan Quan }
1131e098bc96SEvan Quan
vega10_disable_se_edc_force_stall_config(struct pp_hwmgr * hwmgr)1132e098bc96SEvan Quan static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
1133e098bc96SEvan Quan {
1134e098bc96SEvan Quan int result;
1135e098bc96SEvan Quan
1136e098bc96SEvan Quan result = vega10_disable_se_edc_config(hwmgr);
1137e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result);
1138e098bc96SEvan Quan
1139e098bc96SEvan Quan return 0;
1140e098bc96SEvan Quan }
1141e098bc96SEvan Quan
vega10_enable_didt_config(struct pp_hwmgr * hwmgr)1142e098bc96SEvan Quan int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
1143e098bc96SEvan Quan {
1144e098bc96SEvan Quan int result = 0;
1145e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
1146e098bc96SEvan Quan
1147e098bc96SEvan Quan if (data->smu_features[GNLD_DIDT].supported) {
1148e098bc96SEvan Quan if (data->smu_features[GNLD_DIDT].enabled)
1149e098bc96SEvan Quan PP_DBG_LOG("[EnableDiDtConfig] Feature DiDt Already enabled!\n");
1150e098bc96SEvan Quan
1151e098bc96SEvan Quan switch (data->registry_data.didt_mode) {
1152e098bc96SEvan Quan case 0:
1153e098bc96SEvan Quan result = vega10_enable_cac_driving_se_didt_config(hwmgr);
1154e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result);
1155e098bc96SEvan Quan break;
1156e098bc96SEvan Quan case 2:
1157e098bc96SEvan Quan result = vega10_enable_psm_gc_didt_config(hwmgr);
1158e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result);
1159e098bc96SEvan Quan break;
1160e098bc96SEvan Quan case 3:
1161e098bc96SEvan Quan result = vega10_enable_se_edc_config(hwmgr);
1162e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result);
1163e098bc96SEvan Quan break;
1164e098bc96SEvan Quan case 1:
1165e098bc96SEvan Quan case 4:
1166e098bc96SEvan Quan case 5:
1167e098bc96SEvan Quan result = vega10_enable_psm_gc_edc_config(hwmgr);
1168e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result);
1169e098bc96SEvan Quan break;
1170e098bc96SEvan Quan case 6:
1171e098bc96SEvan Quan result = vega10_enable_se_edc_force_stall_config(hwmgr);
1172e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result);
1173e098bc96SEvan Quan break;
1174e098bc96SEvan Quan default:
1175e098bc96SEvan Quan result = -EINVAL;
1176e098bc96SEvan Quan break;
1177e098bc96SEvan Quan }
1178e098bc96SEvan Quan
1179e098bc96SEvan Quan if (0 == result) {
1180e098bc96SEvan Quan result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
1181e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
1182e098bc96SEvan Quan data->smu_features[GNLD_DIDT].enabled = true;
1183e098bc96SEvan Quan }
1184e098bc96SEvan Quan }
1185e098bc96SEvan Quan
1186e098bc96SEvan Quan return result;
1187e098bc96SEvan Quan }
1188e098bc96SEvan Quan
vega10_disable_didt_config(struct pp_hwmgr * hwmgr)1189e098bc96SEvan Quan int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
1190e098bc96SEvan Quan {
1191e098bc96SEvan Quan int result = 0;
1192e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
1193e098bc96SEvan Quan
1194e098bc96SEvan Quan if (data->smu_features[GNLD_DIDT].supported) {
1195e098bc96SEvan Quan if (!data->smu_features[GNLD_DIDT].enabled)
1196e098bc96SEvan Quan PP_DBG_LOG("[DisableDiDtConfig] Feature DiDt Already Disabled!\n");
1197e098bc96SEvan Quan
1198e098bc96SEvan Quan switch (data->registry_data.didt_mode) {
1199e098bc96SEvan Quan case 0:
1200e098bc96SEvan Quan result = vega10_disable_cac_driving_se_didt_config(hwmgr);
1201e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result);
1202e098bc96SEvan Quan break;
1203e098bc96SEvan Quan case 2:
1204e098bc96SEvan Quan result = vega10_disable_psm_gc_didt_config(hwmgr);
1205e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result);
1206e098bc96SEvan Quan break;
1207e098bc96SEvan Quan case 3:
1208e098bc96SEvan Quan result = vega10_disable_se_edc_config(hwmgr);
1209e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result);
1210e098bc96SEvan Quan break;
1211e098bc96SEvan Quan case 1:
1212e098bc96SEvan Quan case 4:
1213e098bc96SEvan Quan case 5:
1214e098bc96SEvan Quan result = vega10_disable_psm_gc_edc_config(hwmgr);
1215e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result);
1216e098bc96SEvan Quan break;
1217e098bc96SEvan Quan case 6:
1218e098bc96SEvan Quan result = vega10_disable_se_edc_force_stall_config(hwmgr);
1219e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result);
1220e098bc96SEvan Quan break;
1221e098bc96SEvan Quan default:
1222e098bc96SEvan Quan result = -EINVAL;
1223e098bc96SEvan Quan break;
1224e098bc96SEvan Quan }
1225e098bc96SEvan Quan
1226e098bc96SEvan Quan if (0 == result) {
1227e098bc96SEvan Quan result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
1228e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
1229e098bc96SEvan Quan data->smu_features[GNLD_DIDT].enabled = false;
1230e098bc96SEvan Quan }
1231e098bc96SEvan Quan }
1232e098bc96SEvan Quan
1233e098bc96SEvan Quan return result;
1234e098bc96SEvan Quan }
1235e098bc96SEvan Quan
vega10_initialize_power_tune_defaults(struct pp_hwmgr * hwmgr)1236e098bc96SEvan Quan void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1237e098bc96SEvan Quan {
1238e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
1239e098bc96SEvan Quan struct phm_ppt_v2_information *table_info =
1240e098bc96SEvan Quan (struct phm_ppt_v2_information *)(hwmgr->pptable);
1241e098bc96SEvan Quan struct phm_tdp_table *tdp_table = table_info->tdp_table;
1242e098bc96SEvan Quan PPTable_t *table = &(data->smc_state_table.pp_table);
1243e098bc96SEvan Quan
1244e098bc96SEvan Quan table->SocketPowerLimit = cpu_to_le16(
1245e098bc96SEvan Quan tdp_table->usMaximumPowerDeliveryLimit);
1246e098bc96SEvan Quan table->TdcLimit = cpu_to_le16(tdp_table->usTDC);
1247e098bc96SEvan Quan table->EdcLimit = cpu_to_le16(tdp_table->usEDCLimit);
1248e098bc96SEvan Quan table->TedgeLimit = cpu_to_le16(tdp_table->usTemperatureLimitTedge);
1249e098bc96SEvan Quan table->ThotspotLimit = cpu_to_le16(tdp_table->usTemperatureLimitHotspot);
1250e098bc96SEvan Quan table->ThbmLimit = cpu_to_le16(tdp_table->usTemperatureLimitHBM);
1251e098bc96SEvan Quan table->Tvr_socLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrVddc);
1252e098bc96SEvan Quan table->Tvr_memLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrMvdd);
1253e098bc96SEvan Quan table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1);
1254e098bc96SEvan Quan table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2);
1255e098bc96SEvan Quan table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx);
1256e098bc96SEvan Quan table->LoadLineResistance =
1257e098bc96SEvan Quan hwmgr->platform_descriptor.LoadLineSlope * 256;
1258e098bc96SEvan Quan table->FitLimit = 0; /* Not used for Vega10 */
1259e098bc96SEvan Quan
1260e098bc96SEvan Quan table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address;
1261e098bc96SEvan Quan table->Liquid2_I2C_address = tdp_table->ucLiquid2_I2C_address;
1262e098bc96SEvan Quan table->Vr_I2C_address = tdp_table->ucVr_I2C_address;
1263e098bc96SEvan Quan table->Plx_I2C_address = tdp_table->ucPlx_I2C_address;
1264e098bc96SEvan Quan
1265e098bc96SEvan Quan table->Liquid_I2C_LineSCL = tdp_table->ucLiquid_I2C_Line;
1266e098bc96SEvan Quan table->Liquid_I2C_LineSDA = tdp_table->ucLiquid_I2C_LineSDA;
1267e098bc96SEvan Quan
1268e098bc96SEvan Quan table->Vr_I2C_LineSCL = tdp_table->ucVr_I2C_Line;
1269e098bc96SEvan Quan table->Vr_I2C_LineSDA = tdp_table->ucVr_I2C_LineSDA;
1270e098bc96SEvan Quan
1271e098bc96SEvan Quan table->Plx_I2C_LineSCL = tdp_table->ucPlx_I2C_Line;
1272e098bc96SEvan Quan table->Plx_I2C_LineSDA = tdp_table->ucPlx_I2C_LineSDA;
1273e098bc96SEvan Quan }
1274e098bc96SEvan Quan
vega10_set_power_limit(struct pp_hwmgr * hwmgr,uint32_t n)1275e098bc96SEvan Quan int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
1276e098bc96SEvan Quan {
1277e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
1278e098bc96SEvan Quan
1279e098bc96SEvan Quan if (data->registry_data.enable_pkg_pwr_tracking_feature)
1280e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
1281e098bc96SEvan Quan PPSMC_MSG_SetPptLimit, n,
1282e098bc96SEvan Quan NULL);
1283e098bc96SEvan Quan
1284e098bc96SEvan Quan return 0;
1285e098bc96SEvan Quan }
1286e098bc96SEvan Quan
vega10_enable_power_containment(struct pp_hwmgr * hwmgr)1287e098bc96SEvan Quan int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
1288e098bc96SEvan Quan {
1289e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
1290e098bc96SEvan Quan struct phm_ppt_v2_information *table_info =
1291e098bc96SEvan Quan (struct phm_ppt_v2_information *)(hwmgr->pptable);
1292e098bc96SEvan Quan struct phm_tdp_table *tdp_table = table_info->tdp_table;
1293e098bc96SEvan Quan int result = 0;
1294e098bc96SEvan Quan
1295e098bc96SEvan Quan hwmgr->default_power_limit = hwmgr->power_limit =
1296e098bc96SEvan Quan (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
1297e098bc96SEvan Quan
1298e098bc96SEvan Quan if (!hwmgr->not_vf)
1299e098bc96SEvan Quan return 0;
1300e098bc96SEvan Quan
1301e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1302e098bc96SEvan Quan if (data->smu_features[GNLD_PPT].supported)
1303e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1304e098bc96SEvan Quan true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1305e098bc96SEvan Quan "Attempt to enable PPT feature Failed!",
1306e098bc96SEvan Quan data->smu_features[GNLD_PPT].supported = false);
1307e098bc96SEvan Quan
1308e098bc96SEvan Quan if (data->smu_features[GNLD_TDC].supported)
1309e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1310e098bc96SEvan Quan true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1311e098bc96SEvan Quan "Attempt to enable PPT feature Failed!",
1312e098bc96SEvan Quan data->smu_features[GNLD_TDC].supported = false);
1313e098bc96SEvan Quan
1314e098bc96SEvan Quan result = vega10_set_power_limit(hwmgr, hwmgr->power_limit);
1315e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1316e098bc96SEvan Quan "Failed to set Default Power Limit in SMC!",
1317e098bc96SEvan Quan return result);
1318e098bc96SEvan Quan }
1319e098bc96SEvan Quan
1320e098bc96SEvan Quan return result;
1321e098bc96SEvan Quan }
1322e098bc96SEvan Quan
vega10_disable_power_containment(struct pp_hwmgr * hwmgr)1323e098bc96SEvan Quan int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
1324e098bc96SEvan Quan {
1325e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
1326e098bc96SEvan Quan
1327e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1328e098bc96SEvan Quan if (data->smu_features[GNLD_PPT].supported)
1329e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1330e098bc96SEvan Quan false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1331e098bc96SEvan Quan "Attempt to disable PPT feature Failed!",
1332e098bc96SEvan Quan data->smu_features[GNLD_PPT].supported = false);
1333e098bc96SEvan Quan
1334e098bc96SEvan Quan if (data->smu_features[GNLD_TDC].supported)
1335e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1336e098bc96SEvan Quan false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1337e098bc96SEvan Quan "Attempt to disable PPT feature Failed!",
1338e098bc96SEvan Quan data->smu_features[GNLD_TDC].supported = false);
1339e098bc96SEvan Quan }
1340e098bc96SEvan Quan
1341e098bc96SEvan Quan return 0;
1342e098bc96SEvan Quan }
1343e098bc96SEvan Quan
vega10_set_overdrive_target_percentage(struct pp_hwmgr * hwmgr,uint32_t adjust_percent)1344e098bc96SEvan Quan static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
1345e098bc96SEvan Quan uint32_t adjust_percent)
1346e098bc96SEvan Quan {
1347e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
1348e098bc96SEvan Quan PPSMC_MSG_OverDriveSetPercentage, adjust_percent,
1349e098bc96SEvan Quan NULL);
1350e098bc96SEvan Quan }
1351e098bc96SEvan Quan
vega10_power_control_set_level(struct pp_hwmgr * hwmgr)1352e098bc96SEvan Quan int vega10_power_control_set_level(struct pp_hwmgr *hwmgr)
1353e098bc96SEvan Quan {
1354e098bc96SEvan Quan int adjust_percent;
1355e098bc96SEvan Quan
1356e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1357e098bc96SEvan Quan adjust_percent =
1358e098bc96SEvan Quan hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
1359e098bc96SEvan Quan hwmgr->platform_descriptor.TDPAdjustment :
1360e098bc96SEvan Quan (-1 * hwmgr->platform_descriptor.TDPAdjustment);
1361e098bc96SEvan Quan vega10_set_overdrive_target_percentage(hwmgr,
1362e098bc96SEvan Quan (uint32_t)adjust_percent);
1363e098bc96SEvan Quan }
1364e098bc96SEvan Quan return 0;
1365e098bc96SEvan Quan }
1366